Design Of A Co-Simulation Platform With SystemC And RTL Hybrid Models

Virtual prototypes can be used for architecture exploration,system integrate verification,and software development,which can effectively promote projects to complete.Although RISC-V is growing rapidly,there is less research on virtual prototypes for RISC-V architecture.Only functional models contained by most of the open-source RISC-V virtual prototypes,which can be used for software development but difficult to apply to architecture design.A hybrid virtual prototype named RV-HVP is designed,which based on an open-source virtual prototype named RISCV-VP.First,a timing model is constructed based on the hardware information of TS-PULP(a custom MCU design based on PULP),which quantifies the clocking effect introduced by pipelining,branch prediction,and Cache.Meanwhile a configurable multi-core simulation system is built to simulate the multi-core computing environment at the embedded edge.A co-simulation interface is designed to provide communicate between the virtual prototype and the RTL model.Three experiments are performed on the designed hybrid virtual prototype RV-HVP.Firstly,the software performance under different Cache configurations is evaluated based on the timing model.The 4k B-4ways cache configuration is verified a better configuration for the PULP architecture;secondly,performance of the 8*8 interconnect is evaluated under the BEEBS benchmark suite.Cross-bar has performance advantage in this scenario;thirdly,the simulation speed of pure virtual prototype,hybrid virtual prototype,and pure RTL model is compared.Compared with the pure virtual prototype,the RV-HVP obtains comprehensive and accurate simulation results for interconnect with 84% overhead.Compared with the pure RTL circuit simulation,RV-HVP can get 56.79 speedup ratio,which demonstrates the simulation speed and accuracy advantages of the hybrid virtual prototype designed in this thesis.