Research On Real-time Reconfigurable OBC For Satellite And Launch Vehicle Integrated Spacecraft

The use of small satellites and small launch vehicles to rapidly provide information on natural disasters to decision-making entities is a viable approach. However, due to limited payload capabilities in small launch vehicles it is necessary to implement spacecrafts using minimal space, weight and power consumption. To address this issue, under the support of the National High Technology Research Development Plan (863), this dissertation presents the Satellite and Launch Vehicle Integrated Spacecraft (SLVIS) concept and focuses on the research and design of an On-Board Computer (OBC) for it.Using a novel approach, the SLVIS integrates the traditional functions of individual satellite and launch vehicle architectures by sharing the same electronic system thus reducing the weight, power consumption and space of the on-board processing system allowing for increased payload capacity of the integrated spacecraft.The SLVIS concept requires a multi-function, high-performance, low-cost, flexible and reliable OBC. This dissertation presents a Real-Time Reconfigurable OBC (RTROBC) based on reconfigurable computing technology. Achieving its architecture and functions by using dynamic reconfiguration and software/hardware co-design technologies allows the RTROBC to control the SLVIS during boost and on-orbit operations. In order to ensure the reliability of the RTROBC, the randomicity of device reliability is considered and a method of reliability validation based on Monte Carlo simulation is proposed. Reliability validation is performed throughout the design of the RTROBC so that the architecture of RTROBC can be improved as a result of the validation.Most fault-tolerant designs that compensate for both temporary and permanent faults for reconfigurable computing system are based on unique laboratory Field Programmable Gate Array (FPGA) devices that are not suitable for operational use. To achieve the characteristics of low-cost the design described in this dissertation uses Commercial-Off-The-Shelf (COTS) FPGA devices. This research presents a dynamic multiplex fault-tolerant method which integrates hardware, time, and information redundancy methods. Applying dynamic double-module reconfiguration, readback, and damage-shield technologies this fault-tolerant method can effectively repair the FPGA from both temporary and permanent faults. Compared to traditional static Triple-Module Redundancy (TMR) systems, the RTROBC fault-tolerant system designed by this dynamic multiplex method offers better reliability and resource utilization.To reduce the high labor and equipment cost and avoid the limit of communication time of traditional mission planning system, this research also addresses the use of automatic mission planning for the SLVIS using the RTROBC architecture. Considering the indetermination of space environment and running states of spacecraft, the mission planning system is described into a dual random digital model using Hidden Markov Model (HMM) and resolved by both a forward/backward iterative algorithm and a Baum-Welch algorithm. The mission planning model is self-improving during operation.The dissertation research develops a semi-physical, real-time simulation environment to display the functions and performance of the RTROBC. Simulations are performed to validate the operation of the RTROBC during SLVIS boost phase and on-orbit operation, validate the ability of fault-tolerant, and also validate the ability of dynamic reconfiguration under automatic mission planning system. Simulation results have shown that the RTROBC can satisfy operation requirements of the SLVIS.