Radiation Effect Mechanism And Reliability In SOI MOSFETs

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce signi?cant charge buildup in these oxides and insulators leading to device degradation and failure.SOI(silicon on insulator) devices are dielectrically isolated. Therefor, these devices have reduced collection volume and p-n junction areas compared with bulk devices. These make it possible to manufacture SOI devices with significantly better SEU(single event upset) and dose rate radiation response from the facts that the active devices are built on top of an insulating layer. Therefore, MOSFETs and ICs based on SOI technology have long been explored for radiation-hardened space and military applications. Simultaneously, SOI materials have the advantage of small parasitic capacitance, high integration density, simple process, fast speed, and small short-channel effects. They are rapidly becoming a main-stream commercial technology.Nevertheless, radiation-induced charges buildup in parasitic ?eld oxides and SOI buried oxides present a series of parasitic structures. Individual transistors processed in these technologies can lessen the advantages of the SOI transistor structure, and represent a tradeoff between bulk-silicon technologies and the transistor isolation of SOI technologies. Consequently, many efforts have been made to reduce these parasitic structures and very high levels of radiation hardness have been achieved.The dissertation is broken down into four sections.The first section provides explanations for these total dose radiation damage mechanisms of the exposed to 60 Co g ray device under different bias con?gurations and measurement conditions, which include its suddenly increasing drain current and a unique upside down bell shape of the body current. Following explanations and examples for how these mechanisms of three Kink effects manifest themselves in the PD(patially depleted) SOI NMOS transistors are provided. A model that describes the back n-channel threshold voltage shift as a function of total dose for the worst-case back gate total dose bias condition is proposed. Last, the combined effects of hot carrier and total dose irradiation in the PD SOI NMOS transistors are studied and the interaction of these two types damage that lead to the transconductance degradation is presented by a qualitative model that divides the damage into two regions.The second part describes process techniques by Si+ implantation techniques included in the buried oxide layer that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate theeffects of trapped charge in the parasitic ?eld oxides. The validity of the proposed methods is proved by several sets of real-measured data.In bulk-silicon technologies charge liberated by an ion strike along the path of the ion can be collected at sensitive circuit nodes from several microns deep within the silicon substrate. So the single event effect in NMOSFET at different drain bias, gate length and striking location is thoroughly analyzed by 2D numerical simulator in the third section. However, bipolar amplification occurs in PD SOI transistors as a heavy-ion strike liberates carriers in the body region of a transistor. A two and three dimensional computer simulation for PD SOI devices is also presented and compared. In the end, the single event effect of H-gate SOI NMOS devices under total dose ionizing is discussed. The result shows the maximum drain current of devices under the same conditions is slight increasing, but the transistors get a significant increase in the drain collected charge with the increasing total dose level.