Study On High Speed Switch System And Their ASIC Frontend Design

ln these years the quick develop1nent of fabric com1nunication technology make the switchsysteln becoIni11g tI1e barrier of lnodern high speed communication network. So study, design andlllanulhcture high speed switch system are very important fOr modern high speed communicationnetwork. Asynchronous transfer mode (A1M) had been specified as the base of the broadbandintegrated services digita1 network by international telecommunication union telecommunicationstandardization sector (lTU-T). One important method of ATM to realize high speed data transferis using cell whose size is tixed. Because of it, ASlC cat1 deal with cell directIy. So ATM switchcal1 switcl1 ceII at high speed, and study on A1'M switch is of great empl1asis in these years. T11eresult of the study has a great signification not only fOr ATM but also fOr other field using highspeed switcll.Tlle goaI of this article is to design a high speed ATM switch system, so there are three parsof tllis articIe.l) Most switcll systems used now are studied. The result of the research of most switcl1system including Time Divided Switch systeln and Space Divided Switch system, and its bufferstrategy indicate that Tilne Divided Switch system can not meet with the data transfer speed infabric when design large scale high speed switch system because of the process of semiconductor.So Space Divided Switch systeln is chosen in our design.2) Clloose the space divided switcl1 fabrics and their scheduling algorithm for l1igh speedswitch systel11 based on analysis and stimulation. The perfonnances of two main space dividedswitch fabrics including Crossbar and Multistage Intercon11ect Network (MIN), including ExtendMuItistage I11terconnect Network (EMlN) are study careful1y. The result of ana1ysis a11dstilllulation of buftbr strategy including input buffer and output buffer explain why using inputbuffer. Because of block in head of line (HOL), input buffer strategy make the whole switchsystem perfOrmances declining drastically at heavy oflbred load, and some improvements of inputbuffer strategy are put fOrward to overcoming tlle head of line block. Virtual output queues (VOQ)is chosen as input buffer Strategy. DPA and iLQF ce1l scheduling algorithms fOr VOQ aresilllulated. The rueslt of simulatiol1 is tl1e base of hardware design.3) Design switch system using EDA based on the result of a11alysis. Because the function ofswitch system is very complicated, some modules are designed by schematics directly, mostmodules are designed by Verilog HDL using EDA technology, synthesized by the Synopsyssoftware. At last a high speed ATM switch system is designed, including VOQ as input bufferstrategy DPA cell scheduling algorithm and Crossbar switch fabric.