Fault-Tolerant Design And Implementation Of Space High Reliability Microprocessor

This thesis focuses on the study of space high reliability microprocessor which is designed for space platforms, such as on-board computer system design and implemention. Space radiant environment is the special factor we should pay attention to when we design space high reliability processor. This thesis research architecture of Leon 3 microprocessor which is conforming to the SPARC V8. Based on Leon 3, a fault tolerance microprocessor is designed aimed at the Single Event Upset efforts. It avoids some magnitude of SEU error. Inject fault in modelsim simulator to verify fault tolerance design. Build FPGA platform to evaluate the cost and compatibility of fault tolerance design.The main contributions in this thesis are as follows:1. It analyses the space radiant environment, gives out several radiant efforts which have impact on the processor. Base on leon3 frame, high reliability fault tolerance architecture is proposed to reject SEU affect.2. Base on implementiong of leon3' pipeline technology, discusses fault tolerance design of register file, proposes many kinds of design strategy. Combining performance with cost implements fault tolerance design of high reliability, low cost register file base on hamming code.3. Base on Cache system, proposes the data reload strategy which using cyclic redundancy codes. Implements the high reliability Cache controller which using cyclic redundancy codes to check error in Cache memory and data reload to correct the error.4. By fault tolerance design of architecture, without consuming very much resource, makes the SEU fault ratio of microprocessor reduce from 0.46 err/device-day downto 4.7788E-9 err/device-day.