The Design And Implementation Of High-Reliable 8051 And Reliability Estimation

In recent years, there has been a rapid increase in the use of computer systems. Most applications require computer systems to work steadily and reliably. This trend has led to critical concerns with the validation of the reliability of the microprocessor, which is the heart of the computer system. Radiation and electromagnetic interference are two typical causes of microprocessor faults. The interference of Single Event Element (SEE) caused by radiation and electromagnetic interference is the focus of current high reliable microprocessor design techniques.Single Event Upset (SEU) phenomenon of SEE will not damage the circuit of the processor, but it can change the logic state of the circuit. As a result, the circuit will work incorrectly and failures will be brought in. SEU is a transient effect and occurs randomly, so it has become the main concern in SEE mitigation techniques of the high reliable microprocessor design. SEU can result in different kinds of fault and lead to microprocessor malfunction. Different function unit in microprocessor has different operational principle, and there are different kinds of Reliability-improving technologies to improve their reliability.First, this paper analyzes how SEU event arises and its environment, and then analyzes how it can affect microprocessor, especially temporal logic circuit and combinational logic circuit.Registers in microprocessor are easily to malfunction under SEU attack. Triple Modular Redundancy (TMR) technique can improve their reliability. But traditional Triple Modular Redundancy (TMR) technique will sample the same fault value at the same time and make registers fault. Enhanced ST-TMR (EST-TMR) is use to improve fault tolerance of both the combinational logic circuit and sequential logic circuit, which enhance the Space-Time TMR (ST-TMR) technique with double edge triggered registers.For ALU, a Berger code detector is added in microprocessor to monitor its operation. Berger code detector use the internal function mapping relationship in different arithmetic and logic operation to detect err during operation. EDAC error detector and corrector have been implemented to improve the reliability of register file and memory during read and write process. Control flow check and context saving restoring is use to harden the control unit. Also safe state machine has been added to harden state register of Multiply and Division Unit (MDU) for operation control.Fault interjection has been applied to check how much the effect of reliability-improving technologies can achieve and the way that fault affects microprocessor operation. Results indicate that when fault duration is shorter than phase difference of three clocks, enhanced ST-TMR can almost mask the SEU in combinational logic circuit and clock line. Slightly enlarge the phase difference can improve effect, but has optimum value. If phase difference is larger optimum value, it will degrade the effect. When fault duration is longer than phase difference will result in fault sampling by two registers and make feedback circuit in fault state for a long time.At last, this paper applies SystemVerilog assertions to fault checking, working with fault interjection to check the effects of reliability-improving technologies applied to circuits. Markov analysis method working with the fault interjection results and implementation of HR8051, analyzes the hot backup system behavior at some assumption which is made to simplify the fault events analysis.