The Research And Analysis Of Topology In Network On Chip

With the development of system-on-chip (SoC), the integration on a chip isincreasing, and shared bus structure commonly used in current chip design has failed tomeet the requirements of System. Network-on-Chip (NoC) appears at this time. The keyidea of it transplants the technology of computer network into chip design instead ofexisting shared structure.Topology is one of the most important fields in NoC design, and it represents theconnection among the node in communication. The choice of the topology structureaffects the performance of system and size of chip seriously. In this paper, we studiedthe topology of NoC, the main work includes the following aspects:For one thing, we analysis the ring, octagon, mesh and torus et al topology andproposed an Octagon-Ring (OR) architecture for the failure in the expansion of highcomplexity and wiring defects. This architecture has8nodes per ring. Every node has4neighbor nodes in inner layer and3adjacent nodes in other layer. In this paper, we givea shortest path routing algorithm for the proposed OR topology. According to thesimulation by the soft ware OPNET, the result prove it have better performance such aslatency and throughput. And it is a simple, flat and symmetrical topology with easierscalability.For another, we give a3D octagon double ring topology based on the3D octagontopology. This topology consults the each node in the light of3D Mesh connection inthe vertical direction to achieve a three-dimensional expansion of Octagon ring structure.In this paper, we simulate and compare the3D OR,3D mesh and3D torus topology, andthe result approve the better performance of3D OR topology in certain circumstance.