Research Of The Fault-Tolerant Methods On TSVs And Buffers Of Three-Dimensional Network-on-Chip

The performance of three-dimensional Network-on-Chip has been greatlyimproved by the benefits from the vertical link design and the scalability ofNetwork-on-Chip. It has a lower power consumption and greatly improving the systemperformance. But it will face the challenges of the increasingly serious reliabilityproblems with the nanometer technology, the current manufacturing process makes theproduct yield of Through-Silicon-Via(TSV) is still low, In addition, as VLSI deviationfragile and easy to aging cause the circuit reliability problems, these factors will affectthe reliability of the3D NoC. Therefore, this thesis will make an intensive study offault-tolerant problems of TSVs and buffers. The main ideas are as follows:This thesis describes the development of integrated circuits and the researchbackground of the3D NoC and2D NoC, and it also introduces the topology, switchingtechnology,virtual channel technology, the basic structures of the router, and the basicknowledge of TSVs.To solve the problem of low yield of TSVs, in this thesis, we propose afault-tolerant vertical link design without redundancy TSVs and packets can betransferred by reuse defect-free TSVs. We also solve transient fault by adding errorcontrol schemes. Experimental results show that the proposed architecture has highreliability, high throughput and low latency.To solve the problem of buffers failure, in this thesis, on the basis of the analysisof buffers fault model, we design a redirection mechanism for the defect-free buffers.And it can dynamically allocates Virtual Channels (VC) and buffer resources accordingto network traffic conditions. Further more, Buffer slots are dynamically allocated toincrease router efficiency. Experimental results show that the proposed architecture hashigh reliability, high throughput and low latency.