Research Of The Fault-Tolerant Method On Network-on-Chip Communication Architecture

With the continuous development of fabricaton technology of the integratedcircuit,the number of transistors intergrated on a single chip and the chip densityare increasing, which enabled the integration of ten to hundreds of pre-designedIPs(Intellectual Property core) on a single chip. The increasing of the number of theIP cores and intensive combinations of homogeneous and heterogeneous moduleson a chip have revealed the significance of on-chip networks (OCNs) design.Traditional bus-based OCN architecture suffers from the issues of poor scalability,low communication efficiency due to non-parallel communication, and powerconsumption and area problem caused by the synchronization of global clock.Therefore, in order to solve these problems, Network-on-Chip(NoC), a newinterconnected architecture was proposed by some experts. Packet basedNetwork-on-Chip has evolved as a new paradigm to overcome these designchallenges and is considered the prime candidate to form the network infrastructureof future MPSoCs with the advantage of high scalability,better performance andlower power. At the same time, as the feature size continues to shrink,the chip indeep submicrom process is more prone to be faulty in the course of production andusage. How to guarantee its effectiveness when the NoC communicationarchitecture is faulty becomes a hotspot in the current research of NoC.This thesis mainly introduced basic knowledge of communication architecturein2D Mesh NoC, and based on this architecture we designed a communicationarchitecture of high reliability. At the same time,we designed a fault-tolerantrouting algorithm for the proposed communication architecture. The main work ofthe thesis are as follows:(1)This thesis introduced the technical background, key issues in researchand current research situation at home and abroad of NoC. NoC based on2D Meshstructure was also detail described. In addition, the basic knowledge such as softand hard failures and the corresponding fault-tolerant technology in the NoC wasintroduced in this thesis.(2) In order to improve the reliability of the NoC communication architecture,we designed a dual-port RNI(Resource Network Interface) with low hardware overhead. Each IP core is connected to two routers by using dual-port RNI based ontraditional2D-Mesh architecture,so that we can get a high reliable NoCcommucication architecture DPA (Dual Port Architecture). The experimental resultsshowed that the DPA architecture has high reliability, while the hareware overheadof this architceture was smaller than other schemes.(3) The proposed DPA architecture enriches the diversity of thecommunication path of the IP core and improves the reliability of thecommunication architecture. Considering to the current fault-tolerant routingalgorithm are just for2D Mesh NoC, we specifically designed a fault-tolerantrouting algorithm for the proposed DPA architecture to make it fault tolerant. Theexperimental results showed that high reliabile DPA architecture, coupled withfault-tolerant routing algorithm, greatly improving the reliability and faulttolerance of the entire communications architecture.