Design Of High Speed Low Power Flip-Flop And Feature Extraction

It is very important to select the appropriate flip-flops structure in very large scale integrated circuit design, also in the design of high speed and low power consumption microprocessor. When the delay of flip-flops occupies the important part in the whole clock cycles, the performance of the flip-flop has an important influence on the clock frequency as in the deep submicron macroprocessor. Flip-flops couple with other units to generation and spread the clock, consumption 20%-40% power of the whole chip. So the research of high performance low power flip-flop plays an important role in the design of circuit. This topic mainly aimed at the research and simulation of the high-performance and low-power flip-flops has made, mainly studied the following aspects of content.1) The design and simulation of the high-performance low-power D flip-flopThere are two kinds of flip-flops designed in this article, the first is a adaptive coupling flip-flop(ACFF), the flip-flop is characterized by low power consumption, compared with the traditional master-slave flip-flop(TGFF) the power consumption reduced by 8.43%, relative to the Transmisson Gate Plulsed Latch(TGPL) reduced by 55.28%; The second is the TGPL, its advantage is more fast. From the simulation of the circuit and layout found that relative to the TGFF about 45% reduction.The backend to check the timing in the physical design is reference the characteristics of standard unit and macro block feature view, after finishing the design and simulation of the designed flip-flop then extracting the view of features, and has carried on the experiment and comparison of different method.2) The design and simulation of D flip-flop test circuitIn order to prove that the designed D flip-flop can work normally, and the temporal characteristic is reliable, in this article test circuit is designed for flip-flops, test circuit is mainly divided into three parts, the first part is the delay(clock to output) measurement module; The second part is the power measurement module; The third part is setup-hold time measurement module(TDC). Delay module error rate is about 7%(5 ps), setup-hold time module precision can reach 1.25 ps, the power consumption module also takes a different turn over rate, has carried on the comprehensive comparison of different design.This topic include the design of the D flip-flop, feature extraction, and the measurement module, the comprehensive analysis on the flip-flop and measurement, in the timing of promotion and improve energy utilization at the same time, also ensure the reliability of the flip-flop.