The Soft Error Tolerant Latch Design Of Integrated Circuits In Nanoscale Technologies

The integrated circuit industry is the core of the information industry, and it is also the strategic industry of the country. With the development of semiconductor technology,the performance of integrated circuits has been improved, but the reliability of the integrated circuit has become more and more serious. When CMOS technology evolving into the nanoscale, supply voltage and stored charge in sensitive nodes are reduced rapidly. The CMOS circuits are becoming more and more vulnerable to soft error induced by radiation.This dissertation aims to soft errors of digital integrated circuits in nanometer technologies. We proposed effective hardened design based on research of existing design for radiation hardened latch. The framework of this dissertation as follows:The STSRL latch is proposed to deal with single event upset in this thesis.Adopting 1P-2N element?% C element and clock-controlled inverters which are the separation of input, the STSRL latch can be able to self-recover when particles strike on any one of its single node. Furthermore, it can be used for the clock gating circuit. Fast path designs and clock-controlled designs are applied to reduce delay and power.Compared to HLR-CG1?HLR-CG2?TMR and HiPeR-CG hardening latches,The STSRL latch reduces 44.40% power consumption, 81% delay cost and 94.20% power delay product,in the meanwhile,reduces 1.80% area overhead.In this thesis we propose the SEDNUTL latch that can tolerate single node upsets and double node upsets by adopting dual modular redundancy fault-tolerance technique.Compared to DOUNT?Delta DICE?DNCS?HRDUNT?NTHLTCH latch, the SEDNUTL latch achieves 90.66% reduction in delay, 14.74% increase in power, 90.27%reduction in power delay product and 16.22% reduction in area on average, compared to the referred same kind of hardening latches. Moreover,its delay is insensitive to process,supply voltage and temperature variations.