The Research On Radiation Hardened Structure Of Digital Integrated Circuit

As technology size is scaling, the susceptibility of circuits to single event effects caused by space radiation is increasing. Especially when the integrated circuit used in aerospace field, single event effect has become one of the main causes of the circuit failure.Domestic and foreign scholars have made a lot of research and proposed a lot of radiation hardened circuit structure. But these structures can only tolerate SEU or SET, and usually can incur great power consumption, delay and area overhead.The main researches of this dissertation are the following:This thesis describes the radiation and describes the radiation effects, then focuses on single event transient and single event upset.Analysis of the mechanism of action and effect on integrated circuit.Then we talk about current radiation hardened technology and compared the advantages and disadvantages of these technologies.In view of the existing radiation hardened technology cannot tolerate SEU and SET at the same time and have a great influence by the process variation.A soft error tolerant robust latch named HLTL is proposed. By means of separating the gate of NMOS and PMOS transistors in an inverter to build redundant storage nodes, the latch could be immune to SEU. Taking advantage of filtering pulse design, the latch can mask SET. HSPICE simulation results show that the proposed latch has advantages on fault tolerance performance and overheads when comparing with the reference designs, and has less sensitive to process and temperature variation.In view of the existing radiation hardened circuit structure have a large power consumption.In this paper a high-performance soft error tolerance latch (DSH-CG) is proposed uses space and time redundancy technology. The latch is composed of two internal redundant modules and an output stage which consists of a C-element and a keeper. It not only can filter SET pulse propagated from the previous combinational logic stage, but also be fully immune to SEU. The simulation results by SPICE, compared with the similar design,DSH-CH have a smaller power consumption and can be applied to the clock gating circuit.