Design And Implementation Of SATA Controller Based On FPGA

With the advent of the data explosion era,the requirement for high-speed transmission and real-time storage of massive data is becoming stricter,whether in the military field or in the civilian field.As far as radar signal processing is concerned,it is necessary to store large amounts of raw data to verify and optimize algorithms.Therefore,it is of great importance to design a device that can store mass of real-time raw data.The high-speed Serial ATA(SATA)interface is a mainstream high-speed storage interface standard which can realize high-speed transmission and real-time data storage.Therefore,the SATA interface developed on FPGA is studied in this thesis.SATA evolved from the parallel ATA(PATA)interface standard.Compared with the PATA interface,the SATA interface has obvious advantages such as fewer interface pins,fast transmission speed,good reliability,strong stability,convenient application and hot swap.The main studies about the SATA standard protocol in the thesis are summarized as the following:1.According to the different abstraction levels from the serial bit level to the command level,the overall architecture and hierarchical architecture of the SATA controller consists of the physical layer,the link layer,the transport layer and the command control layer are designed in the thesis.Then,a new operation mode which operates the control interface by reading and writing the start sector address is proposed.2.According to the SATA standard protocol,the main functions,structure,external interface and internal working sequence of the command layer,the transport layer,the link layer and the physical layer are designed in the thesis.(a)By analyzing the interactive process of frames in SATA protocol data transmission,a command layer consists of logical block address(LBA)calculation module and read/write control module is designed and implemented.(b)By analyzing the transport layer protocol,a transport layer consists of frame establishment module,frame receiving analysis module and controlling module is designed and implemented.(c)By analyzing the link layer protocol,a link layer consists of cyclic redundancy check(CRC)module,scrambling/descrambling module and control module is designed and implemented.The main functions of the link layer are descrambling frame,check and controlling the frame transfer through the original language.(d)By analyzing the physical layer protocol,the physical layer consists of high-speed serial transceiver and out-of-band signal(OOB)module is designed and implemented.The main functions are to achieve the initialization of the device after power-on.3.By adding some peripheral test modules to the controller,an overall test platform of the SATA controller based on FPGA is designed in the thesis.Then,the correctness and the reliability of the design are verified by simulation on the platform.The final tested data show that the SATA IP CORE designed in the thesis based on FPGA meets the requirement of the protocol.The designed SATA IP CORE has the advantage of convenient application,high integration,low cost.The design will make the development more conveniently and quickly so that the mass storage development will be simpler and meet the needs of the market better.