Emulation Design Of High-speed Serial Interface Module Based On FPGA

In the modern society, the amount of information grows explosively. As the development of new technologies, such as networks, multimedias, and so on, the demand for bandwidth and speed increases rapidly. Because of the clock jitter and skew, as well as the PCB wiring's difficulty, the parallel transmission faces the design limits of the speed's further promotion. While the high-speed serial communication technology, with its wide bandwidth, outstanding anti-interference performance and simple interface, is rapidly replacing traditional parallel technology and becoming the mainstream in the communication fields.For the two kinds of high-speed serial interface circuits, which are very popular and have great development potential, this paper mainly researches on the high-speed linkport and Rocket I/O, and takes Xilinx most latest Virtex-5 FPGA as platform to do the simulation design. The main work of this paper is taking the low-cost phased array radar signal processor as the platform, and doing the research on the high-speed linkport based on LVDS and Rocket I/O high-speed serial interface based on CML on one of the signal processing boards. Firstly, do the programme design, the functional simulation and the timing simulation in the software of FPGA. Secondly, the most important thing is to debug on the hardware platform. The method of hardware debugging is to link the DSP TS201's linkport with the FPGA's simulated high-speed linkport for the data's transmission. Received data is the same as sent data, so the result proves the correctness of the high-speed linkport design. And the method of Rocket IO GTP transceivers'hardware debugging is to use the data's loopback. After loopback, received data is the same as sent data, so it proves the correctness of the Rocket IO high-speed serial interface design.