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Investgation Of Hot Carrier Reliability For BCD-based 70V Lateral DMOS

Posted on:2018-02-18Degree:MasterType:Thesis
Country:ChinaCandidate:X F RenFull Text:PDF
GTID:2348330542969225Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
The power management integrated circuit(Power IC)is involved in a wide range of application such as Automotive Electronics system,Power Over Ethernet(PoE)system and Display driver,and BCD(bipolar-CMOS-DMOS)process has been the most advanced process for Power IC due to its higher integration and power density.The lateral double-diffused metal-oxide-semiconductor(LDMOS)is regarded as the major device in the Power IC.Besides,the LDMOS fabricated by the deep-submicron process suffers a severe hot-carrier-induced issue.Therefore,the in-depth research of hot-carries-induced degradation of BCD-based LDMOS is of great significance.The maximum substrate current(Isub,max)stress and maximum operating gate voltage(Vg,max)stress are chosen as the hot carrier stress.The degradation mechanism of LDMOS is investigated by the method of TCAD simulation,the electrical parameter degradation test and charge pumping test.For Isub,max stress,the dominating degradation mechanism transfers from interface states generation along the surface at the bird's beak to hot holes trapping into the oxide beneath the edge of real poly-gate with the increasing stress time.For Vg,max stress,the degradations mechanisms are always identified to be hot electrons trapping in channel region and the interface states generation at the bird's beak.In addition,the influence of the structure parameter of the device on the hot carrier reliability has been investigated.The increase of length of channel region,accumulation region and poly-gate will improve the electrical parameter degradation.The research on the hot-carrier-induced degradation impacted by field-oxide fabrication concludes that the device with deposited filed oxide has a similar degradation mechanism with the one based on the Local Oxidation of Silicon(LOCOS),while the degradation mechanism of the device based on the Shallow Trench Isolation(STI)is only dominated by the interface state generation at the corner of the shallow trench.Based on the investgation of degradation mehanism,three kinds of novel device structure including non-uniform-doping drift region,secondary field oxide and recessed poly-gate are proposed to optimize the hot-carrier-induced degradation.The optimized device with recessed poly-gate performs the 36%decrease of the Ron degradation.
Keywords/Search Tags:BCD process, LDMOS, Electrical parameter degradation, Hot carrier reliability, Optimization
PDF Full Text Request
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