Study On Hot Carrier Effect And Nonlinear Idsat Degradation On 55nm CMOS Process Technology

In the explosive changes of contemporary science and technology,the integrated circuit has penetrated into all aspects of people's work and life.Demand for integrated circuit chips is growing,and how to improve the integration of the chip and performance has become the main direction of the industry.With the development of mature process,MOSFET device feature size has been narrowed in proportion significantly,and the hot carrier effect intensified by short channel effect is increasingly highlight which results in the reliability bottlenecks of the circuit system.With the advancement of technology nodes,MOSFET devices degradation induced by hot carrier effect is complicated,the traditional mechanism models to evaluate the actual reliability engineering encounters challenges.This paper first introduces the mechanism of MOSFET hot carrier effect and the test evaluation method in the industry.Then the factors that affect the hot carrier effect are summarized such as device size,electrical parameters,testing temperature and stress model.Finally the effective method to improve the hot carrier effect on the process technology is exploited.Studies show that the linear relationship between MOSFET channel length and TTF exists under the 1/Length X and logarithmic Y axial.Initial MOSFET electrical parameters impact on the degradation induced by hot carrier effect and I_dsatsat degradation becomes severer with the increasing of I_dsatsat initial value.The selection critical point of test temperature and test stress mode for nMOSFET channel length is 0.08?m.When channel length is above 0.08?m,Max substrate current mode at25?is selected.On the other side,V_g=V_d mode at 125?is selected.Gate oxide process optimization,LDD process optimization and anneal process optimization have obvious impact on inhibiting hot carrier effect on 55nm CMOS process technology.Subsequent discussion concentrates the phenomenon of nonlinear hot carrier effect degenerate in the evaluation test,then the new degradation mechanism and reasonable test evaluation method is proposed.Traditional hot carrier effect degradation model considers the whole process of device degradation mechanism is constant under the same stress mode and stress strength,which results in the device electrical parameters linear degradation using the power law fitting to stress accumulation time.According to the measured data,the degradation mechanism of MOSFET on 55nm CMOS process technology is no longer dominated by one mechanism and degradation curve is nonlinear.For nMOSFET devices,degradation is mainly affected by falling electrons in gate oxide in the early stage of degradation,and then the acceptor interface traps become the main factor of I_dsatsat degradation.For pMOSFET devices,the falling trapped electrons in gate oxide also play a major role in the early stage of degradation,and then the donor interface traps gradually dominate the degradation.Nonlinear degradation can't be observed when gate oxide thickness of pMOSFET decreases to certain value.Actual test condition should be confirmed basing on actual degradation.Due to obviously changeable fitting slope in the whole degradation process,fitting slope basing on a certain time period would get wrong result.The influence and significance of this study is engineering experience of 55nm technology according to the hot carrier effect test,which gives other technology node for follow-up development guidance and reference.