Research On Reliability Evaluation Method Of Integrated Circuit Based On PTM

As CMOS transistors shrink to nanoscale dimensions,the integrated density of circuit rises sharply,resulting in an increase in the incidence of soft errors,which in turn has increased the failure rate of the circuits constructed by nano-scale transistors.Therefore,it is particularly important to evaluate the reliability of the integrated circuit during the early design process.It is helpful for the circuit designer to compare and evaluate different circuit designs based on the calculated reliability measurements so as to obtain an optimal circuit design that is not susceptible to soft errors.This paper mainly studies the reliability evaluation methods of large-scale integrated circuits..Firstly,the research status of integrated circuit reliability evaluation is reviewed,the main factors affecting the reliability of the circuit were analyzed,and then describes the existing design techniques for improving reliability of circuit.For the sequential circuit,this paper selects several classical reliability evaluation methods for comparative research,and analyzes the advantages and disadvantages of these evaluation methods.The traditional PTM method can evaluate the reliability of the entire circuit.It builds the overall PTM of the circuit based on the known basic gate failure rate,and then combines the input distribution to calculate the reliability of circuit.However,since the computational complexity of this method increases exponentially with the circuit scale,the PTM method is obviously impractical if the scale of the circuit is very large.But,considering the high accuracy of the PTM method and its suitability for combinational circuits,this paper chose to improve it.Firstly,a circuit reliability evaluation method based on error probability propagation model is proposed.This method loads the actual error probability of the logic gate on the connection wire and calculates the correct output probability of the logic gate one by one until the output gate.The reliability obtained at this time is the overall reliability of the circuit.Experiments shows that the improved method proposed in this paper effectively reduces the computational complexity and is suitable for the reliability evaluation of large-scale circuits compared with the traditional PTM method.Secondly,the failure of the wire is an important factor that affects the reliability of the circuit,but the traditional PTM method only considers the failure rate of the logic gate in the calculation.Thus,a circuit reliability evaluation method considering the probability of wire failure is proposed to solve this problem.In the case of logic gate failure,the influence of wire failure on circuit reliability is considered.An error PTM is established for logic gates and wires based on the PTM definition,then calculate the output probability one by one.The experiments shows that this method is less complex and can accurately assess the reliability of the circuit under the influence from logic gates failure and the wire faults.