Estimation Method Research For Soft Error Reliability Of Logic Circuits

Very Large-Scale Integrated Circuit technology is an important part of modern electronic information technology,and it plays a great role in promoting the development of science and technology,national economy and national defense construction.With the application of deep sub-micron and nanometer technology,the integrity in chips has increased continually,and circuits design has become more and more susceptible to radiation.The soft errors induced by high energetic particles affect the circuit reliability severely.Evaluating the reliability of logic circuits under the influence of soft errors can assist the fault tolerance design,and it is a hot research spot in academic and industry.From the basic theory of reliability and analysis of signal probabilities and circuit topology,this thesis attempts to research the logic circuits affected by soft errors,and proposes some efficient soft error reliability estimation methods of combinational logic circuits and sequential logic circuits.These estimation methods can be used for calculating the reliability of large scale circuit and even very large scale circuit accurately,and can also be used for locating the logic elements which are sensitive to soft errors.The innovative works of this thesis are as follows:(1)According to probabilistic gate model,a soft error reliability estimation method of combinational logic circuits based on signals' probabilities is proposed.All signals' probabilities from primary inputs to primary outputs are calculated under the stimuluses of some given input vectors first,and then the soft error reliability of circuit is analyzed combining fault simulation.Compared with the probabilistic transfer matrix method and the idea of circuit partition,the proposed method can calculate the reliability of combinational circuits under specific vector and random vectors quickly and accurately,and it can be used for soft error reliability estimation of large scale combinational circuits as it needs shorter time and less space.(2)The signal correlation of logic circuits is the main factor for the calculation of signals' logic values.In order to reduce the deviation and make the soft error reliability estimation results of logic circuits more accurate,a signal probability calculation method which uses the probability formula and polynomial arithmetic is proposed.The signal probability of primary output can be obtained under the stimulus of any input vector by reducing order,further calculating the reliability of circuits through random input vectors.The proposed method can be used for reliability estimation of medium scale circuits and large scale circuits because it needs shorter time and is more accurate than the existing methods.(3)A reliability range calculation method of logic circuits based on probability statistical model is proposed.The correctness of every logic gate is regarded as random event and the reliability of circuits can be decomposed into the sum of products of some conditional probabilities and corresponding coefficients.On the basis of this,every coefficient can be calculated by using the property of Bernoulli distribution and the reliability range of circuits can be obtained based on the primitive component.Theoretical analysis and experimental results show our method is accurate and efficient.(4)A soft error reliability estimation model of sequential logic circuits is established and a reliability estimation method based on error propagation probability matrix is proposed.The error propagation probability of logic gates and flip-flops in current clock cycle is represented with four EPPMs,and then the error propagation probability in multi-cycle is calculated by customized matrix union operation.Considering the characteristics of Bernoulli distribution,the reliability of sequential circuit is estimated.Experimental results on ISCAS'89 benchmark circuits show that the proposed method is accurate and efficient,and it is better than the existing methods.(5)In addition to evaluating the impacts of logic circuits by soft errors,accurate analysis of the soft error susceptibility for circuit elements is an important part of the fault-tolerant design.The proposed method uses four error propagation probability matrices to represent the error propagation probability of logic gates and flip-flops in current clock cycle.Based on the predefined matrix union operations,the susceptibility of circuit elements in multiple clock cycles can be evaluated.Experimental results on ISCAS'89 benchmark circuits show that our method is efficient,and it can be used for assisting the soft error tolerant design,reducing the testing and maintenance costs and improving the reliability of circuits.