| This thesis presents a serial backplane receiver with adaptive blind decision feedback equalization (DFE), designed in 0.35 mum TSMC process, which can operate up to 4Gbps over 1.2 m long FR-4 (typical isolation material used for making Printed Circuit Boards---PCB) based PCB channel, which includes discontinuities due to the packaging and backplane connectors.; To maximize data rate that can be supported by the receiver, the DFE is achieved in look-ahead manner where each input symbol is sampled with two biased comparators---one biased high as if the previous symbol was low and the other biased low as if the previous symbol was high.; The biased comparator is implemented by adding two bias transistors to the sense amplifier based flip-flop (sense amplifier followed by an SR-latch), also know as Strong-Arm flip-flop. The inherent input hysteresis of the Strong-Arm flip-flop was reduced by an order of magnitude with a simple modification of the standard SR-latch.; DFE coefficient calculation is not performed on every consecutive received sample, which significantly reduces the design complexity and power consumption. Adaptation algorithm is not only used to adjust DFE coefficient, but also to compensate for attenuation of the transmission line. |
