| Increases in backplane data transfer rates are accompanied by worsening signal integrity problems, principally ones of channel attenuation, reflection and crosstalk. The collective effect of these appears as inter symbol interference (ISI), a major factor limiting transmission distance and speed.; Both linear and nonlinear equalizers use knowledge of a data stream's history to eliminate ISI effects, but the nonlinear ones are able to enhance the desired signal while not amplifying noise. Decision Feedback Equalization (DFE), a kind of nonlinear device, is one of the most effective means of dealing with the ISI problem.; A new half-rate pipelined multi-tap CMOS DFE structure is proposed in the present work. Starting from an initial circuit concept, a MATLAB behavioral model having fixed post-tap coefficients is constructed. The model is used to verify the design's functionality and to determine parameters needed for a transistor-level design.; The proposed DFE is composed of two pipelined signal paths with cross-coupled feedback in which linear equalizing amplifier circuits and phase detecting circuits are used to process the even- and odd-indexed bits of the data stream. The outputs of the two branches are then reintegrated to recover a data stream at the original rate. Since each branch only has to work at one-half of the incoming data rate, the new DFE is called a half-rate DFE, or HRDFE.; The design was verified by HSPICE simulation, with TSMC 0.18mu m CMOS process parameters being assumed. The results of a post-layout simulation involving a 34 inch FR4 backplane demonstrate eye opening increases and acceptable BER at data rates at least as high as 8 gigabits per second. Only 12.2 milliWatts is consumed from a 1.8 Volt power supply. |
