Modeling and design of low-voltage ferroelectric memories

The migration of FeRAM's to low operating voltages (1V and below) is resulting in new challenges in the modeling and design of ferroelectric memories. This thesis presents a Verilog-A model that accounts for the voltage-dependent switching-time (VDST) of ferroelectric capacitors evident at low voltages. The VDST Model is adaptable to the switching characteristics of various ferroelectric capacitor technologies, compatible with popular circuit simulators such as Spectre and Nanosim, and exhibits a 23 times speedup over previous work. The model is then used in the design of a low-impedance FeRAM read scheme that maximizes the achievable sense margin at low voltages. The proposed Charge-Mirroring Read Scheme is implemented in a 16-kbit FeRAM testchip targeted for a 0.18mum/0.35mum CMOS/PZT process. Based on simulation results, it achieves a 70% reduction in area, 40% reduction in read access time, and 400% increase in memory bandwidth in comparison to previous work.