The Research On Method Of Soft Error Protection For Nanoscale Integrated Circuits

With the continuous progress of integrated circuit technology,the integration and performance of the chip have been greatly improved.The process size of CMOS transistors has been continuously reduced.At the same time,the supply voltage has been continuously reduced and the critical charge of the circuit node has decreased,which makes the chip more sensitive to single event effects caused by radiation.Especially for integrated circuits used in the aerospace field,the single event effect has become one of the main reasons for the failure of integrated circuits.The single event effect has two types.One is single event upset in sequential logic circuit and the other is single event transient in combinational logic circuit.Scholars at home and abroad have done a lot of research about the project and put forward many circuit structures which have ability for radiation hardening.However,most of these structures can only tolerate SEU or SET,and usually face problems such as largely area,highly power consumption,and largely delay overhead.Based on the above problems,the dissertation proposes two hardened latch structures with low power consumption,fast delay and high reliability,which is based on the analysis of existing latches.Firstly,A SEU tolerant hardened latch with cross-connection is proposed.The Four three-input-split inverters in the latch are connected to form a storage unit,which can steadily ensure to latch the logic value of the circuit node.In addition,the use of the C-element structure as the output stage effectively prevents SEU from occurring at sensitive nodes in the structure.The HSPICE simulation experiment shows that Compared with the other hardened latches in terms of transmission delay,area overhead and power,the proposed structure achieves 6.19%reduction in area overhead,44.43%reduction in delay,11.20%reduction in power and 51.44%reduction in power delay product on average.Secondly,a low-power radiation hardened latch considering process variation is proposed.The latch utilized a high-level signal to control the clocked inverter to constitute the feedback loop,which greatly reduced power consumption,and add a C-element at the end of the latch to achieve the effect of protecting the SEU.In addition,the SET is filtered by adding a delay unit between the input node and the transmission gate.Compared with the similar SEU/SET tolerant latches,the proposed structure achieves 3.90%increase in area overhead,37.34%reduction in delay,55.01%reduction in power and 75.22%reduction in power delay product on average.Delay and power are less affected by process,voltage,and temperature variations and performance is more stable.Figure 35 table 7 reference 65...