The Research On Soft Error Tolerance Technology Of Integrated Circuit In Nanometer Technologies

With the continuous progress of semiconductor manufacturing process, the integrated circuit having experienced upgrading performance and reducing power consumption, but the reliability of the integrated circuit also facing a serious threat. The integrated circuit becomes increasingly sensitive to environment and the soft error caused by energetic particle is increasing due to continuous declination of technology node. The soft error serious threat the normal operation of the integrated circuit, which reduces the reliability of the system. In order to improve the reliability of the integrated circuit, aim at the soft error in the integrated circuit, we have a deeply research on the circuit level fault-tolerant technique. The framework of this thesis as follows:Firstly, we introduce the relative factors which influence the reliability of the integrated circuit, indicating that as a representative of single event effect, single event upset and single event transient are the main causes of the soft error. Expounded the relative conception and production mechanism of soft error in integrated circuit, we have a detailed analysis of soft error, including its production mechanism, propagation characteristics and protective methods.Secondly, after knowing the usual method of fault-tolerant techniques, we have a further research on it and emphasize on the common soft error tolerate technologies in combinational logic unit and temporal logic unit and analyze the merits and demerits of different technologies. By comparing various methods, we bring two low-overhead Hardened Latches CFL-SET and SINV that immune to single event upset.The CFL-SET latch employs C element which has the function of filtering to build a feedback loop, we add a clocked C element to prevent the propagation of SEU effects through the latch output. The simulation results of HSPICE show that the CFL-SET latch provides the equivalent reliability as a TMR-latch and occupies 50% less area, produces 92% less delay, consumes about 67% less power and 97% less power delay product than the TMR-latch.The SINV latch employs 4 inverters whose inputs are separated to constitute an interlocked structure, we add a clocked C element on the output of the latch to block the transient fault. The simulation results of HSPICE show that, compared to previous hardened latch designs, the SINV latch achieves 61% reduction on average in terms of delay,11% reduction on average in terms of power and 59% reduction on average in terms of power delay product (PDP) with 40% area overhead on average.Finally, for the two Hardened Latches that mentioned in this thesis, we employ HSPICE to make detailed fault injection and use PDP to evaluate and compare two Hardened structures with existing structures. The experiment improves its reliability and the two Hardened Latch structures can not only increase the reliability of circuit, but also with lower power dissipation and area dissipation.The high-reliable Hardened Latches in the paper enrich and provide the practical method for the fault-tolerant technique in integrated circuit, which have a great importance.