Acceleration SIFT Algorithm For Surface Defect Detection Of Tempered Glass Based On FPGA

In the process of transparent tempered glass production and quality inspection,defect analysis is particularly important and the market demand is huge.With the continuous improvement of image processing technology and the rapid development of FPGA in the field of image processing,at present,most of the research and development of optical measuring instrument equipment companies adopt FPGA scheme to meet the needs of industrial image sampling frame rate and image processing frame rate.In this paper,based on FPGA,the accelerated SIFT(scale invariant feature transform)algorithm design and experimental research were explored in the surface defect detection of tempered glass.Taking the defect detection of tempered glass as the application background,the accelerated SIFT algorithm was proposed as an optimization scheme of image processing and feature recognition.It mainly includes:(1)Feature points are described by vector-scale method based on the data output by SIFT algorithm,and it is required to integrate support vector machine(SVM)for complete identification and classification of defect labels;(2)Using Xilinx vivado platform for FPGA design;(3)xilinx zynq7020 chip is used to accelerate image processing;(4)The modeling and testing of SVM at the software level are studied.Main research contents of this paper:1.Debug Mohr grating,use Altium Designer to design steel mesh,calculate the size of steel mesh,debug the actual width of backlight fringe and light effect,so that the actual shooting of toughened glass defects has been significantly improved.2.Use SIFT to generate feature description vector and Python simulation SIFT algorithm,and observe the feature extraction situation and data results of the intermediate variables run by SIFT algorithm.The division results of modules and structures corresponding to the subsequent hardware design are sorted out.Meanwhile,according to the simulation results of python code running,the redundant structures can be deleted.verilog is used to design SIFT algorithm using FPGA to accelerate the algorithm design.It includes designing the content of algorithm module according to the structure division of module,using modelsim for debugging and calculation;The redundant structure of the algorithm is deleted to minimize resource occupancy and dimension of feature description.In addition,the design results are simulated,and the extraction information of feature points and feature description output of feature points can be obtained by inputting the actual shot pictures.3.In order to test the feature description of SIFT algorithm,the distinction of different defect labels,using SVM modeling research method,will get the feature description information,using the feature description vector to establish a SVM model database,and then training the SVM model,the model running results analysis found that the linear SVM recognition rate is about 80%.4.In order to build a complete hardware structure and organize the hardware framework,appropriate sensors and main control equipment are selected.After communication debugging,a good match between the driver and the test equipment is completed;Then transplant the Linux operating system and use the kernel driver.The industrial-grade usb camera transmits the data to FPGA through the linux kernel driver,and uses the AXI interface to let FPGA receive the complete data stream.Finally,the interface matching between the algorithm layer and the driver layer is completed,and the operation of the designed algorithm is debugged in the actual hardware environment.The experiment shows that Verilog’s acceleration algorithm design for SIFT achieves the expected effect.When the system calculates the image at the calculated frame rate of 60 frames per second,the SVM model presents a good recognition accuracy(about 80%)for the output of SIFT hardware acceleration algorithm to the scale.This design has certain theoretical research and practical application value.