Integration Switched Current Curcuits Test Technology

Switching Current (Switched Current SI) technology is a simulation sampling data signal processing technology completely adopt digital CMOS process technology which has been bring forward by the late 1980s . It uses MOS transistors to maintain its current capacity, through storage the drain charge in the gate capacitance of its open gate Switched Current technology does not require switching linear capacitance and high-performance operational amplifiers and compatible with standard digital CMOS process completely. It also has the advantages of low-voltage, high-speed, broadband, small size. Since it advent related scholars of home and abroad are arosed high degree of concern, and has been relatively rapid development. Switched current technology is a new simulation sampling data signal processing technology follow the switched-capacitor technology, as well as an important direction of development of digital / analog hybrid integrated VLSI Implementation.However, concerning the testing aspect, the test techniques proposed for analog circuits are not readily applicable to SI circuits. To date, little has been published on the test of SI circuits. Literatures describe reconfiguration of SI biquadrates filters for test, Built-In Self-Test (BIST) scheme, Design Function Test(DFT), testing methods Based on the DC signal pipeline structure AD switching current converter, restructuring of current mirror structure use clock change and contrast between the DC input signals and output. The proposed techniques suffer of being applicable only to some specific structures, and these methods only use DC and low-frequency parameters for implicit functional testing, the tolerate range and failure or error in parameters have not been discussed.This paper summarizes the existing analysis and test methods of switching current circuits, developed a system simulation software on switching current non-ideal factors , investigate the fault model of Switch current circuits, Several test theory put forward. Its main tasks are:1. Invesitigate non-ideal characteristics of switched current circuits systematacially, discussed the shortcomings of various simulation tools for the switch current circuit simulation analysis. A complete set of SIMULINK models based on non-ideal of switched-current circuit is presented, which allow exhaustive behavioral simulations of switched current to be performed. The proposed set of models takes into accounts most of the SI memory non-idealities, such as charge injection errors, conductance ratio error, settling error, kT/C noise, and a description of the relationship between error and parameters of MOS FET is presented.2. Research on the test difficulties on current analog circuit, Aim at switch current circuit form and the entire structure of transistors, a more comprehensive fault model is put forward, which is applicable for multiform test methods. Chohort MOS parameters is studied and analyzed in instance. The basic functions and features of switching current ASIZ simulation software is introduced.3. Switched current circuit on the nodal analysis and the sensitivity analysis based on transconductance are investigated, whitch can provide choice for optimized performance parameters and the results forecast in the design process. Based on mismatch effect and circuit performance deviation error caused by current scaling, under the conditions of given the transconductance random error absolute or statistical error is calculated, further achieve the error tolerance, whitch can be used to test circuit products.4. A built in Pseudo-Random sequence testing for testing embedded switched-current filters is described. The generation approach of Pseudo-Random sequence and the match for z functions of switched-current filters is analyzed and calculated. Based on the correlation function of the performance space to identification signals space acceptable tolerances space tolerance of mapping methods is discussed, And the relative Confidence level of testing technical is analyzed.5. Combining the time and frequency location and multiple-scale analysis of Wavelet transform (WT) with the nonlinear mapping and generalizing of Neural Network, an efficient defect-oriented parametric test method for switched-current integrated circuits is proposed. Include the following steps: sinusoidal input to the analog circuits as stimuli and its output was sampled in frequency and time domain to collect training data for neural network. Chohort sensitivity analysis is applied for selecting the test models. To reduce complexity of the neural network, the collected data was processed by WT to draw energy features, generate fault features using wavelet decomposition to process the response drastically reduce the number of input fed to the Neural Network, simplifying its architecture and minimizing its training and processing time for detecting hard-detectable catastrophic defects in switched-current circuits.