Harware/Software Codesign Research On Hdtv Integrated Source Decoder Chip

HDTV (High Definition Television) is developed from analog television to achieve high resolving power of image quality. HDTV integrated source decoder is a key component of high definition television receiver. In this dissertation, using HW/SW (Hardware/Software) co design strategy, we develop the SOC (System On Chip) mainly focusing on the following three fields: system partition synthesis and verification.The design process of this SOC is to map decoding algorithms for TS (Transport Stream), video and audio into processor design space. In this dissertation, a new HW/SW co design technique is designed for HDTV SOC: After analyze the transport packet syntax architecture and decoding algorithm, system is first divided, then a new HW/SW synthesis technique is proposed: based on modeling of the algorithm, some new instructions are extracted to reduce the program size and complication, as a cost, only few hardware is added to support the new instruction set.In this dissertation, a RISC-based developing system (VM: Virtual Machine) is constructed in hardware description language-verilog. It works as a HW/SW simulation platform to co simulate function blocks if this SOC. Cycle-based instruction model guarantees the co simulation and implementation of hardware and software; Flexible-extended instruction set assures the processor upgrade; Adequate hardware abstraction accelerates the system's simulation speed; Friendly user debugging interface provides the software-like simulating environment. The above synthesis technique and RISC core is co verified in this VM.RTOS (Real time operating system), which is designed as system software for this SOC, has a design problem that its overhead of software process scheduling conflicts with real-time requirement from data exchange in multimedia chip. In this dissertation, using HW/SW co design technique, a new RTOS HW/SW synthesis method and co-processor based system architecture is proposed. By divide part of RTOS software into hardware, above real-time problem is solved and software size is reduced to relax memory bottleneck in SOC.