A Study On VLSI Architecture Of Image Sequence Coding Based On Wavelet

The compression & coding of the digital image sequence is the basis of the imagetransmitting and storage. The wavelet transform is suitable for such image codingbecause of such characteristic as the multi-resolution representation. However, thewavelet image coding needs huge computation, it should be implemented withhardware for real-time coding, which will run with much lower power and occupysmaller dimension. The design of the VLSI of the wavelet image coding will befollowed as the developed algorithm mode.In this thesis, the wavelet image coding algorithms and their VLSI architecture arestudied, which include the lifting schemes hardware architecture, zero-tree codingalgorithm and its hardware implement and variable size macroblock motionestimation hardware architecture. For verifying these hardware architectures, all kindsof Verilog HDL models of the coder are programmed, and a demostration PCBmodule based on FPGA has been built up.This thesis achieves the following three innovative results:1) The thesis presents a new parallel array 2-D discrete wavelet transform (DWT)hardware architecture based on lifting schemes. The biorthogonal LS9/7 wavelet filteris adopted in this architecture, and according of the filter, separate column wavelettransform and row wavelet transform hardware architectures are presented. In thelifting schemes architecture of this thesis, a line buffer array is employed in realizingthe 2-D parallel wavelet transform;and a kind of tree fix point shift multiplier basedon the CSD multiplication is presented, which can distinctly reduce the hardwareresource. The lifting schemes architecture of this thesis is optimized in multilevelpipeline design way to speed up and achieve higher hardware utilization.2) A new fast no list SPIHT (FNLS) algorithm and its hardware architecture areproposed for wavelet coefficients coding. This algorithm utilizes two flag mapsinstead of three lists of SPIHT algorithm, which can distinctly reduce the memoryrequirement. Additionally, FNLS algorithm incorporated the insignificant-coefficientpass and refine pass in one pass, and so simplifies the scan processes of SPIHT coding.This thesis presents FNLS hardware architecture in detail, which can encode thezero-tree set and coefficients separated from zero-tree set in parallel.3) A new variable size macroblock motion estimation method and correspondinghardware architecture are presented during the study of sequence images motionestimation. In this method, firstly, sub-macroblocks motion vectors are searched, andthen those sub-macroblocks are incorporated in bigger size blocks on the basis of thesimilarity of the adjacent macroblock motion vectors. The sub-macroblocks motionvectors method adopts local full search, according to which a sort of parallel arrayarchitecture is proposed in this thesis. The array architecture utilities 16 processingunits to search 16 sub-macroblocks motion vector at same time so as to speed themotion vectors search.