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Study On The Multi-Pipeline Reconfigurable Computing System

Posted on:2007-11-10Degree:DoctorType:Dissertation
Country:ChinaCandidate:Y S YinFull Text:PDF
GTID:1118360182986694Subject:Precision instruments and machinery
Abstract/Summary:PDF Full Text Request
The improvement of VLSI technology has leaded to a rapid development of field programmable logic devices such as FPGAs since late 1980's. Today, the hybrid reconfigurable computing system that couples the traditional processor with the reconfigurable hardware is becoming a mainstream. As a new computing paradigm, the reconfigurable computing is recognized as the third path in the computing history, which has become one of the worldwide research hotspots.However, most previous studies on the hybrid reconfigurable computing were not involved with the integrating multiple pipeline-arrays in the same system, nor there a systematic approach to the reconfigurable pipeline-array either. This dissertation studies and develops a new hybrid reconfigurable computing system that has multiple pipeline-arrays, that is MPRS (Multi-Pipeline Reconfigurable System). Its architecture and executing behavior as well as the mapping method are discussed in this dissertation.At first, an architecture model and an executing model of MPRS are developed to build a complete computing system as the basic research platform. The system includes the behavior level description of MPRS simulator, the programming environment and verification environment. How to integrate together the host, the reconfigurable coprocessor and the main memory is considered. And details of the coprocessor including processing unit and interconnection are designed in hierarchy style. Further more the encoding format of the configuration word is defined. As a special feather, MPRS supports the virtual pipeline computing, so a method based on "configuration slice" is brought forward for analysis and design of the virtual array. This method has become the foundation of the coprocessor design and the input/output data arrangement in application programs.Then, a primary study on the automatic design of MPRS is also related in this thesis. A framework of co-compilation for the reconfigurable computing paradigm is proposed and the focus is the systematic approach to the MPRSarrays. To do this, a DGRV is defined, then the basic problems of automatic mapping, such as objective functions and design constrains, are analyzed. With development tools and MPRS simulator, several typical applications are tested and their performances are compared against an existing quasi-MIPS. In the last place, some additional experiences are also mentioned, followed by suggestions for future research.
Keywords/Search Tags:Reconfigurable computing, Multi-pipeline, Virtual array, DGRV, Automatic mapping, Systematic approach
PDF Full Text Request
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