Research And Design On Reconfigurable Pipelined Array System

This paper describes a reconfigurable pipelined array system, which is applicable in large data computing. The array communicates with the main processor through the AMBA interface and improve the computing speed.The paper introduces the architecture of RPAS. The RPAS architecture have two prominent features:1.The context is transported through context router to Array, and each context is corresponding to a pipeline step. By controlling the context router, we can implement dynamic context of the array. Compareed to the traditional way which CPU directly control the input of context, RPAS cost much less load on CPU. 2. RPAS adopts reduced connecting network and isomery prosessing element based on the study of mass DSP algorithm, that reduces the area and complexity of the RPAS.At last this paper explains the execution process of 2D-DCT and SAD arithmetics, which function frequently and cost a majority of time during H.264 coding and decoding. The simulation results show that RPAS can achieve six times or much higher performance than general processor, and make a balance among complexity, area, performance and compatibility.hange programs. It is the center of CERNet in east China region, through computer networks, SJTU has faster and closer connection with the world.