Study On Process And Reliability Of High Power LED Packaging And Through Silicon Via3D Packaging By Simulation And Experiment

Solid state lighting, in terms of high power light emitting diodes （LEDs）will be thefourth illumination source to substitute the incandescent lamp, fluorescent lamp and highpressure sodium lamp. The quality and reliability issues of the high power LED packagingare important for its applications. Three-dimensional packaging technology with throughsilicon via (TSV) is one of the key emerging trends in the field of microelectronicpackaging. However, the TSV processes have been demonstrated still to be at the R&Dlevel and there are still many technical challenges. Otherwise, due to great coefficient ofthermal expansion (CTE) mismatch between the filled metal and silicon, highthermo-mechanical stresses will be induced under the thermal loading during thefabrication processes and operation, which have significant effects on the performance andreliability of the device. Therefore, it is urgent need to carry out the processes optimizationand reliability design for the high power LED packaging and the TSV based3Dpackaging.Some key packaging processes and reliability issues of the high power LEDpackaging and TSV3D packaging are focus on in this study. Multi-physics couplingsimulation models were established to investigate the thermal ultrasonic wire bondingprocess, thermal shock reliability of the high power LED packaging, as well as theelectrochemical copper plating process, thermo-mechanical and electro-migrationreliability of the TSV3D packaging. Some experiment works include materials propertytesting, processes development, reliability validation, and failure analysis were conducted.The detailed contents of this thesis include: (1) The viscoelastic properties of silicone used in the high power LED packagingwere characterized by the dynamic mechanical analyzer (DMA). Based on the generalizedMaxwell model, six-order Prony equation was fitted with the testing data.Nanoindentation test with the continuous stiffness method (CSM) was conducted to thecopper pillars filled in the TSV in order to obtain its mechanical properties. The testingresult shows that the average elastic modulus of the copper pillar is116.8GPa and theaverage hardness is1.7GPa. The plastic properties of the copper pillar were also obtainedby fitting the load-displacement curve of nanoindentation through the simulation of theindentation process.(2) A thermo-mechanical transient dynamic finite element framework was developedto simulate the copper and gold thermal ultrasonic wire bonding processes in the highpower LED packaging. The dynamic deformation, stress-strain distribution, andtemperature evolution during the bonding process was obtained. The results show that asthe ultrasonic vibration amplitude, friction coefficient between the ball and bond pad, andthe bonding force increases, the plastic deformations on the bond pad will increase, whichis benefit to bonding formation. But at the same time, the stresses in the ohmic contactlayers of the electrode structure also increase, which may induce the peeling or cracksdefects and even repture of LED chip. Due to the higher hardness of copper wire, largerenergy must be input during the bonding process. Therefore, during the copper thermalultrasonic wire bonding process, the bond pad, ohmic contact layer, and the LED chip willbe induced higher stresses and strains. The process parameters of copper wire bondingshould be controlled more carefully than the gold wire bonding.(3) The reliability of the application specific LED package (ASLP) module wasvalidated by the thermal shock environmental reliability test. Catastrophic failurehappened to some ASLP testing samples and the failure mode was found to be the opencircuit failure. Fluorescent penetrant inspection was conducted to the ASLP samples. It isfound that the delamination defects occur at the interfaces within the ASLP module underthe loading of thermal shock. The decapsulation analysis was conducted to thecatastrophic failure ASLP samples. It is shown that the fracture failure happen to thewedge joint of the bonding wire. A fluid-solid coupling thermo-mechanical model usingnonlinear time and temperature dependent material properties was established to investigate the thermo-mechanical responses of the ASLP during thermal shock testing.The results show that the temperature gradients within the ASLP module exceed79℃and100℃during the rapid cooling and rapid heating stages of the thermal shock testingrespectively. With the effects of the temperature gradients, the maximum equivalent plasticstrain of the gold wire is2.1times higher than that with the isothermal assumption. Thepotential failure position changes from the wire neck to the wedge joint of the bondingwire with the effects of the delaminations at the interfaces within the ASLP module.Silicone with low elastic modulus and CTE is strongly recommended for the LEDpackaging which can significantly enhance the reliability of the bonding wire underthermal shock loading.(4) An electrochemical plating model was established to simulate the bottom-to-upthrough via copper plating process of TSV. The results show that with the single sidesputtering and bottom-to-up copper plating processes, the growth mode of the copperplating layer is upward perpendicular to the sidewall of the through via, which can avoidthe generation of void defects. With the Bosch DRIE process, the through vias with6:1aspect ratio were etched on the bare silicon wafer. SiO2insulating layer was fabricatedwith the thermal oxidation process. The Ti adhesion-barrier layer and Cu seed layer weredeposited with the single side sputtering process. In addition, the bottom-to-up copperplating process was carried out and copper pillar with no voids defects was successfullyfilled in the through via. Mechanical grinding and chemical mechanical polishing (CMP)for the wafer thinning was conducted and the silicon wafers with60um TSV structureswere successfully thinned to50um thickness.(5) Thermo-mechanical model was established to calculate the residual thermalstresses of the TSV. The micro-Raman spectroscopy was introduced to measure theresidual stresses and make a validation of the thermal residual stresses calculation. Theeffects of the structure parameters of the TSV on the thermal stresses were investigated.The results show that the maximum thermal stresses increase with the diameter of the TSVand the silicon thickness has the limited effects. The thermal stresses in the siliconbetween TSVs increase with decreasing of the pitch due to the stress overlap effects. Thethermo-mechanical reliability of the TSV stacked-dies3D package was studied by theglobal-local finite element simulation combined with the design of experiment (DoE) method. The influences of the package structural parameters on the reliability performancewere analyzed. It is found that the thickness of the silicon interposer has the mostimportant impacts on the fatigue life of micro-solder joint between the stacked dies andnormal solder joint between the silicon interposer and the FR4substrate. The diameter ofthe copper pillar plays the most critical roles in the determination of the fatigue life ofcopper pillar and the reliability of Cu/SiO2interface.(6) An electromigration simulation model, which considers the effects ofelectro-migration, thermo-migration, stress-migration, and chemical-migration, wasestablished to investigate the mass diffusion phenomenon of the TSV under the currentloading. Through the analysis, the electrical, thermal, stresses and atomic concentrationfields of the TSV structure under the loading of high current density were obtained. Theresults show that the hydrostatic stress gradient has significant contributions to themigration of copper atoms. The positions where the voids and hillocks defects may begenerated were predicted through the copper atoms concentration distributions calculation.