Research On The Packaging Process Of Power Devices Integration Based On Panel Level Packaging Technology

With the development of power electronics technology,the traditional packaging scheme has been gradually unable to meet the performance requirements of power devices.Most of the new packaging technologies cannot reduce the process difficulty and cost while improving performance,which hinders their batch production.Regarding to the abovementioned problems,based on the panel-level packaging technology,a hybrid power devices integrated packaging process is proposed in this paper.The process flow and packaging structure are designed,and the electrical,thermal and mechanical performance of packaging structure are simulated and analyzed by finite element software,and the steps of the process are verified by experiments.The purpose of this paper is to explore a power devices integrated packaging process with excellent product performance,low process difficulty,low cost and batch production.The research contents are as follows:(1)A power integrated packaging process based on panel-level packaging technology is proposed.The gate and source of power chip are separated by a special plastic structure,and a window is opened on the surface of the source.According to the characteristics of small gate and large source of the power chip,the gate adopts wire bonding to reduce the process difficulty,and the source adopts redistribution layer to reduce parasitic parameters and improve heat dissipation capacity.(2)Taking Dr MOS as the packaging object,the packaging process flow and structure are designed under the package design specification.The process flow design includes three flow plans: in plan 1,the gate adopts wire bonding,the source adopts drilling and copper plating;in plan 2,the gate adopts copper plating after wire bonding and laser grinding,the source adopts copper plating after wire bonding;in plan 3,the gate and source adopt laser drilling,photolithography and copper plating.The packaging structure design includes lead frame drawing,die attaching drawing,wire bonding drawing,redistribution layer pattern design and overall packaging structure design.(3)Through the corresponding calculation module of the finite element software,the parasitic parameters of the three packaging structures are extracted,the heat dissipation capacity is analyzed,and the thermal stress and warpage are verified.The simulation results show that the gate parasitic parameters of the plan 2 is the best,the source parasitic parameters of plan 1,3 are the best;the heat dissipation capacity of plan 3 is the best,and the warpage of plan 1 is the best,and the three plans all meet the design specifications.After a comprehensive comparison of the process difficulty and the performance,plan 1 is selected as the packaging flow,and combined with the relevant research results,the factors affecting the structural performance are simulated and analyzed.The results show that in a reasonable range,the thickness of the redistribution layer has a great influence on the parasitic resistance and warpage,but has little effect on the parasitic inductance,junction temperature.(4)Under the guidance of simulation analysis,each step of the process flow is verified on the basis of owning equipment and materials.The experiment includes die attaching process,wire bonding process,molding process,redistribution layer process and cutting process.The experimental results show that the task of each process is achieved,and the process is feasible.A hybrid power integrated packaging process with special molding is studied in this paper,and the process is analyzed and verified by simulation and experiments,which has a certain guiding significance for developing in the new power devices integrated packaging process.