Research And Implementation Of High-speed Digital Camera Image Compression Processor

Along with the development of avigation and astronautics, high-resolution andhigh-frame rate digital camera payload is widely used in all fields of the nationaldefense and space sciences. The contradiction between the magnanimous data of rawimage and the limitation of transmission bandwidth and storage capability is more andmore serious. High-speed, high-efficiency and high performance image and vediocompression has been necessary. This paper focuses on the aerial and space imagecompression, and mainly researchs the theory and implementation of JPEG andM-JPEG image compress algorithm based on DCT and CCSDS algorithm based onDWT.Firstly, the high-resolution image enhancement theory before compression isintroduced. An adaptive high-resolution image enhancement algorithm and anotherenhancement algorithm in compression domain are present. Both methods have niceeffect and low complexity, and are very suitble for implementing on FPGA. Theefficient FPGA hardware architectures of image enhancement are proposed. Theresult of experiment indicates that the enhanced image is better than original imagefor machine vision and human vision system.Secondly, the JPEG baseline standard is discussed, and the implement of JPEGencoder on FPGA is propsed. Considering the specialty of high-resolution imagecompression, a novel structure of the codec is designed, which processes the real-timeimage and uses the hardware resource effectively. The function and performance ofJPEG compression processor are validated on FPGA. The result is elicited that theJPEG encoder has the image compress quality near to the quality of software, and canprocess the image with the resolution max to64K×64K, and can compress a frameimage of8176×6132in0.5second.High-speed M-JPEG compression has been researched in this paper too. On thebase of JPEG, the M-JPEG encoder is developed. The experiment result proves that the system not only can compress the vedio of640×480@100fps real time but alsohas the capability of processing higher resolution image or higer frame rate imagesequence.The CCSDS image compression algorithm which based on DWT is developed forspace image. In this paper, the recommendate method is study, and the algorithm issimulated use C code. A novel architecture based on lifting wavelet transform toimplementing9/7integer forward discrete wavelet transform on FPGA is proposed.The line-based architecture performed the3level9/7DWT in parallel way. Wholearchitecture is optimized in the pipeline and with lower system resource use and lessstore access time. Then the CCSDS image compress recommendation is comparedwith JPEG2000. The resolution is analysed, and it can be concluded that the CCSDSimage compression has the compress quality near to the qulity of JPEG2000under thecondition of lower encoder complexity.At last, combined with process of design the aviation digital camera, the strctureof the camera, the electronics sub-system and the interface design were presented.Then, the implemention and simulation of the image input interface, SDRAM controlinterface and data transmission interface were introduced. All of them are the bases ofthe platform of algorithm validation.The JPEG image compression processor and the DWT transform architectureimplement on Altera Stratix II FPGA EP2S30F672I4and the QuartusII software. TheM-JPEG encoder is demonstrated on the Xilinx ISE9.1platform and the Virtex4FPGA XC4VLX40F668C10.