Low-Cost And High-Quality Testing Methods For Delay Faults In Digital Systems

With the increasing density of very large scale integrated (VLSI) circuits and thedevelopment of deep sub-micron technology, VLSI testing becomes more and more dif-ficult. Functional testing methods are not sufcient to guarantee the correctness of thecircuits; therefore, delay fault testing is an essential step for modern VLSI circuits. Testpower, volume, and time are the major test cost parameters that must be minimized whileachieving the desired level of fault coverage. For delay testing, these problems becomemore and more complex, therefore, we propose new methods to solve these problems.We make the following contributions:Previous low-power methods mainly include design-for-testability (DFT)-basedmethods and X-filling methods. These methods are very efcient in reducing test powerfor stuck-at fault testing. However, most of them cannot apply to delay testing directly.We want to propose new approaches to reduce test power without loss of test quality:(1) The use of only a subset of scan cells to capture responses in a cycle may causecapture violations, thereby leading to fault coverage loss. In order to restore the originalfault coverage, new test patterns must be generated, leading to higher test-data volume.In this paper, we propose a scan-cell clustering method that can support multiple capturecycles in delay testing without increasing test-data volume.(2) Partition the circuits into many parts and test each part independently can re-duce test power, however, it may make some testable faults in standard broadside testinguntestable. A new test application scheme called partial launch-on-capture (PLOC) isproposed to solve the problem. It allows only a part of scan flip-flops to be active in thelaunch cycle and capture cycle. In order to guarantee that all testable faults in the stan-dard broadside testing can be detected in the new test scheme, extra eforts are requiredto check the overlapping part. Therefore, a new scan flip-flop partitioning algorithm isproposed to minimize the overlapping part.(3) DFT-based methods can reduce test power efciently, but they need hardwareoverhead. X-filling methods can efciently reduce test power with low overhead. How-ever, traditional X-filling methods cannot be reused in the linear decompressor basedcompression (LDC) environment. In this paper, we propose a virtual circuit model to make the linear decompressor transparent to the external testing. As a result, existingX-filling methods can be reused to reduce test power. Sufcient experimental results arepresented to demonstrate the efciency of the proposed method.Test data compression is a much more difcult problem for launch-on-capture (LOC,for short) delay testing because test data for LOC delay testing is much more than thatof stuck-at fault testing, since LOC delay fault test generation in the two-frame circuitmodel can specify much more care bits which is hard to do compaction and compres-sion. A new scan architecture is proposed to compress test stimulus data, compact testresponses and reduce test application time for LOC delay fault testing. Sufcient con-ditions are presented for including any pair of scan flip-flops into the same group forLOC transition, non-robust path delay and robust path delay fault testing. Test data forLOC delay testing based on the new scan architecture can be compressed significantly.Sufcient experimental results are presented to show the efectiveness of the method.Among the methods for delay testing, broadside testing is widely used for its easilyimplementation, but the fault coverage is low. This paper presents a new method forimproving transition fault coverage in hybrid scan testing. These techniques are based ona novel test application scheme, in order to break the functional dependency of broadsidetesting. Experimental results show that fault coverage based on the proposed method iscomparable to enhanced scan.