The Verification Of At Speed Testing Based On On-chip Clock Circuits

Integrated circuit at an unprecedented impact on social progress in many areas,including consumer electronics,automotive electronics,medical electronics and even in the military.In the consumer electronics and automotive electronics,how to meet people's product portability,versatility,high reliability requirements have become popular.From the integrated circuit designer views,in order to achieve these requirements,means that the circuit need to do more optimization in the feature size,complexity,frequency and other aspects;From the chip tester views,those challenges also can't be ignored,especially with the working frequency improvement,the traditional design of the testability program has been not to solve related problems that caused by the timing problem.Therefore,at speed test technology came into being,that is,tester applied to the test vector and observe the response in the actual operating frequency,which could detect the delay fault.This paper mainly introduces the three parts including at speed high frequency clock circuit,test vector generation and test vector verification.For the at speed high frequency clock circuits,mainly on the clock control circuit optimization,which consists of three parts: Switch_Inst,Pulse_Filter,and Register_Filter.the Switch_Inst module used to select the high-frequency clock in the scan mode and obtains the first part of the high-frequency clock.In order to save the test cost and the test time,the Pulse_Filter part selects the high-frequency clock obtained by Switch_Inst,finally we get high-frequency clock including seven cycles;In order to increase the flexibility of the circuit,users could use the Condition command to achieve related cycles in the Register_Filter circuit.The optimized clock control circuit needs to meet the following requirements: each clock domain within the module can be controlled separately,which is helpful in coverage rate when the circuit is in capture mode,the circuit should choose out correct clock pulse;The slow clock and fast clock switch must be accurate;multiple clock domain share a PLL,reduce the area overhead.For the generation of test vectors,we describe how to generate Stuck at and Transition test vectors in detail,and focus on the three issues that are design rule check,fault coverage rate and mismatch simulation,which are concerned with DFT Tester.Finally we use VCS tools verified the generated test vector to ensure the validity of the test vector.In this paper,the final at speed verification is carried out in a 14 nm SOC chip's audio system module,including at speed test circuit insertion,test vector generation and test vector verification.This module's maximum operating frequency of 307.3MHz,containing 68,000 registers,more than 50 blocks of memory.The experimental data show that at speed testing using on-chip clock circuit,while meeting test coverage,greatly reduces test time and improves test efficiency.