Study On IC Implementation And Sampling Methods For Low Power Energy Metering

Reducing power consumption of energy metering ICs could decrease extra power loads generated by energy meters on power grid. The life of backup batteries in energy meters could also be extended. Higher level of anti-tampering sensitivity and lower hardware cost of meters could be achieved too.An IC implementation of the time-domain integral algorithm of ordinary energy metering was given. Computing capability requirements and circuit flip rates were reduced by converting the algorithm into multirate data processing. According to calculation types and progressively reduced data rates, a digital signal computing unit with specific instructions and architecture was designed. Controlled by the multirate computing FSM besides reusing computing resources, all calculation tasks were completed with circuit flip rate of33.288%. The instruction set was designed just according to calculation tasks, thus there is less redundant circuits and lower power consumption is achieved.The result of metering performance test meets the design specifications. The known process implemented by other mainstream MFEs is0.18μm. The designed chip was manufactured in TSMC0.25μm process. The digital current dissipation of the designed chip is comparable with that of the mainstream MFEs. If implemented in same process, the digital current will be half of that of the mainstream MFEs. Some energy metering ICs applying this design method have been in mass production and have been shipped tens of millions of chips.Current researches of harmonics energy measurement mostly focused on post process of sampled sequences, depending on sophisticated algorithms, and required powerful digital signal processors to carry out. For synchronous sampling methods, higher calculation requirements or complex sampling clock generation circuit was presented.According to oversampling ADC’s characteristics, a non-uniform synchronous oversampling method used to measure harmonics was proposed, from the perspective of less computation, simpler circuit, lower power consumption and oriented for IC implementation. Principle of the non-uniform synchronous oversampling clock generation by DDLL was explained. Relationship between each design parameter and their effects on sampling results were analyzed. Distribution and amplitude of sampling noise and spectral leakage introduced by sampling were identified. Modulation on harmonic signal’s amplitude and phase was determined. How to choose the number of sample points for FFT was also derived.The requirements on frequency resolution of sampling clock are reduced by clock’s oversampling and non-uniform property. Number of delay cells in DDLL is significantly reduced and the structure of DDLL is simplified.Oversampling ratio, probability distribution and variation period of sampling clock frequency in both oversampling and down-sampling stages were properly designed to suppress the impact of spectrum modulation by sampling noise. The generated non-uniform clock can be treated as synchronous clock tracking the fundamental in statistical meaning.The final down-sampled data can be treated as uniformly sampled and synchronous ones. FFT can be directly applied, no extra work of sampling noise and spectral leakage elimination needed. Position of harmonics in spectrum won’t vary any more so that fixed compensation of system attenuation in gain can be carry out, which lowers design requirements on down-sampling low-pass filters. All these characteristics bring low power consumption.When ND=11, the overall sampling noise and spectral leakage is nearby or smaller than-120dB which is the quantitative noise floor of ADC.The larger ND is, the smaller measurement error will be got.Regarding the non-uniform and synchronous nature of the sampling clock, a QSRL fundamental frequency measurement method based on traditional quadrature demodulation was proposed. The impact of clock frequency variation is eliminated. Contrary to phase or frequency error in PLL and AFC, the loop control variable is input signal frequency over output frequency. QSRL is equivalent to an open-loop system, with higher stability and shorter response time.Both the calculation of phase difference and the low-pass filter to cancel beat frequencies between fundamental and harmonics bring limitations to fundamental frequency measurement. These issues will be studied more in future work.