The Research On High Resolution Time To Digital Convertion For Quantum Mmunication

Quantum information has been developing rapidly in recent years, which is a new interdisciplinary subject combining quantum physics and information science. Quantum communication is the most matured research direction. The fundamental laws of quantum mechanical guarantee the unconditional security of the communication, which will essentially enhance communication security. With the help of the stable low-loss transmission channel of free-space between satellites and ground, one can even realize a global quantum communication network.The single photons are often used as information carriers in quantum communication, such as the quantum key distribution (QKD). It’s necessary to detect the single photons and record their arrival time accurately. The communication parties often far away separated and have independent reference clocks. So it’s essential to establish high resolution time synchronization among them. The system timing jitter can directly influence the quantum bit error rate (QBER) and the final key rate. A high precision time to digital converter (TDC) is necessary and can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate.In this thesis, the requirement of TDC in quantum communication was analyzed. A variety of TDC techniques are researched and successfully applied in QKD and good experimental results are obtained.This thesis mainly includes the following3items.Firstly, A high resolution TDC based on the FPGA’s carry chains used as tapped delay lines was implemented. Its high resolution (Bin size) of50ps with precision (RMS) less than50ps, low dead time (30ns) and large dynamic range (167ms) can well meet the requirement of the QKD experiment in the near ground. Taking full advantage of the FPGA’s flexibility, the multi-channel TDC and some other necessary modules in the QKD system are integrated in a single FPGA, such as random data module, laser diode(LD) control module, system control logic, etc. This remarkably improves the system’s integration. With single photon detectors (SPD) and quantum laser diodes, a complete electronic system for QKD was developed. Using this QKD system, three independent QKD experiments were carried out with the system operated on a turntable via a public free-space channel of length40km, a floating hot-air balloon at20km, and over a96km link with about50dB loss, respectively. The experiments provide direct and full scale verification towards ground-satellite QKD. In this system, a high resolution time synchronization system was also developed which can be widely used in QKD. The synchronization system is based on the high resolution FPGA-TDC, and the pulse per second (PPS) signals of the GPS and a synchronous laser light setup are employed.Secondly, to meet the special requirements of payload in satellite, such as high reliability, a wide range and high resolution TDC was designed, which is applied to a actual satellite-ground QKD experiment. As the FPGA-TDC, which is based on SRAM technique, has no experience in the space environment and can be easyly damaged by single event effects (SEE), we use an ASIC chip TDC-GP1, which is more reliably. But the chip cannot meet the experiment requirements as it’s short measurement range and long process time. We combined an FPGA and the TDC-GP1chip together to implement a new TDC. The time interpolation method is used; The FPGA measures the course time and the TDC-GP1measures the fine time. This new TDC’s Bin Size is380ps and RMS is less than250ps, with measurement range can be expanded to671ms. The dead time is1.15us. The TDC is being used in a payload for QKD.Thirdly, in the future satellite-ground quantum entanglement experiment with a long-distance high-loss channel, the TDC’s resolution should be higher. So a in-depth research on tapped delay line TDC in FPGA was conducted. A novel multi-chain multi-measurement average TDC structure was proposed within FPGA. The new TDC is flexible to achieve a balance between the dead time and logic utilization, with higher resolution. With theoretical analysis, model simulation and bench-top tests, we researched the timing performance of the new TDC on the variety of the chain number (M) and the measurement times (N). When using8chains (M=8) and4times (N=4) measured on each chain, the RMS was tested to be7.4ps and the bin size could be as low as1ps, with the dead time is only42ns. Besides, a fast improved fat tree encoder was implemented in the new TDC, which can finish the ultra wide non-thermometer code to binary code encoding process within just one system clock cycle. An encoding time of8.33ns was achieved for a 276-bit non-thermometer code to a9-bit binary code conversion. The encoder could be widely used in delay chain based FPGA TDCs.The key innovation points are listed as follows,1. A high resolution FPGA-TDC was applied in quantum communication, which improved the system performance. Meanwhile, The system’s integration was enhanced and the cost decreased. In the experiment, we also developed a high resolution time synchronization system which can be widely used in QKD.2. A reliable TDC based on TDC-GP1and FPGA was designed, which has wide range(671ms), high resolution(380ps) and small dead time(1.15us). The TDC is being used in a payload for satellite-ground QKD.3. A novel multi-chain multi-measurement average TDC structure was proposed, which can further improve the timing performance, resulting the bin size and RMS both less than10ps. Besides, it is flexible to achieve a balance between the dead time and logic utilization. This TDC can be widely used in QKD. A fast improved fat tree encoder was implemented in the new TDC, which can finish the ultra wide non-thermometer code to binary code encoding process within just one system clock cycle. This encoder could be widely applied in delay chain based FPGA TDCs.