Research On Time To Digital Conversion Technology Based On Field Programmable Logic Device

Time-to-digital conversion technology is the cornerstone of many current scientific research,and has played an important role in many fields such as quantum information,medical imaging,laser ranging and so on.In some specific applications,the performance of Time to Digital Converter(TDC)directly affects the performance of the whole system.In this thesis,based on Field Programmable Gate Array(FPGA),the time to digital conversion technology is studied,and two design schemes based on clock phase division method and buffer delay chain method are discussed.Finally,a time to digital converter with a resolution of sub-nanosecond is realized.The main contents include:(1)The basic principle of time-to-digital conversion technology is introduced,including a variety of concrete implementation of analog method and digital method,which provides theoretical support for subsequent design.On this basis,the performance index of time-to-digital conversion technology is further introduced,which provides index reference for subsequent design.The basic principle of FPGA is described,including the main structure,the programmable principle and the basic development flow.The implementation and application process of FPGA are introduced in detail,and the analysis of timing constraint,which is important in temporal logic design,is also mentioned.(2)The TDC is designed based on the time-to-digital conversion technology and the basic principle of FPGA.Firstly,the design is based on the clock phase division method,the combined measurement scheme of "coarse measurement" and "fine measurement" and the overall system architecture are clarified,and then the process is sorted out and code writing is carried out.After the design is completed,the system is simulated and tested.The design resolution is 625 ps,most measurement errors are 50 ps,and the maximum measurement error is less than 675 ps.The design scheme based on buffer delay chain method is similar to the clock phase division method,the problem of uneven buffer delay is solved by manual placement and routing.The design resolution is 410 ps,and the maximum measurement error obtained by functional simulation is 310 ps.After the core measurement module is completed,the data transmission module is designed to realize the multi-byte data transmission based on UART protocol between the FPGA and the PC host computer.(3)A test environment was built to physically test the two designed TDC.The measurement error of TDC based on clock phase division method is less than 353 ps at200 MHz operating frequency.Further attempts were made to increase the operating frequency to 400 MHz,and the error was further reduced after compensation.The design resolution is 312.5 ps,test results are consistent with the expectation,and the average measurement accuracy is 166.8 ps.The resolution of TDC based on buffer delay chain method is 246.8 ps and the accuracy is 270 ps,the differential nonlinear range and integral nonlinear range are(-0.43,1.30)LSB and(-0.49,3.19)LSB,respectively.