Research On So C Implementation Of Low Level Processing For Object Detection In Infrared Imaging Guidance

Infrared(IR) imaging detection technology has strong anti-interference capability, high detection precision, good concealment and reliability, which makes it a major means of guidance for precision-guided weapons. As a core part of IR imaging guidance weapons, an IR imaging guidance information processing system performs the task of detecting and recognizing targets in complex IR background. With the development of IR detection technology, real-time information processing faces more challenges: the exponential rise of input data rate due to IR sensors with higher resolution, higher frame rate and multi-channel imaging; the rise of the intelligence level of signal processing due to automatic target recognition(ATR) requirement and the miniaturization and integration requirement due to tight size weight and power(SWaP) budget. System on chip(SoC) technology put almost all the functions of an electronic system into a single chip, performing signal capture, transform, storage, processing and input/output on a single die. It is an attractive candidate for IR imaging guidance information processing system. Intellectual property(IP) cores are the foundation and core of a SoC chip, determining its functionality and speed of data processing. Image pre-processing needs of an IR imaging guidance image processing SoC chip is studied and non-uniformity correction(NUC) and global motion estimation(GME) algorithms for IR focal plane array(FPA) are developed, together with the corresponding IP cores. The main contributions are given below.For the NUC of IR FPA, a new NUC method combing linear and non-linear filters is proposed first. Compared with other NUC methods based on least mean square(LMS), the proposed method converges much fast and mitigates the ‘ghosting' effect better. A mean filter with large mask size is used when the level of fixed pattern noise(FPN) is high, taking advantage of its smoothing capability to quickly lower the FPN level. When the FPN drops to a low level, a Sigma filter with small mask is used instead. The edge-preserving capability of the filter helps to suppress the ‘ghosting' effect caused by the smearing of edges. The Sigma filter is also utilized for adaptive adjustment of the iteration step and detection and replacement of abnormal pixels like dead pixels and pixels corrupted by impulse noise. This method is of low computational complexity, which makes it fit for hardware implementation.For the GME of IR image sequence, a fast method based on feature region is proposed. This method solves the problems faced by gradient-based GME methods: high computational complexity and high memory bandwidth requirement. In a hierarchical framework, corner points are detected on the top level Gaussian pyramid image. Only the pixels in local regions centered on the corners(called feature region) are used in the GME iteration. Since the feature regions contain prominent 2-D structure, not only the number of pixels used for GME is significantly reduced, the GME procedure also achieves less aliasing influence, faster convergence and higher estimation accuracy. After GME at an upper level is finished, feature regions with the largest motion estimation error are found and the corresponding corner points are eliminated from the GME of the lower level. By doing so, robustness to large moving target is achieved, together with lower computation complexity. Blur images due to fast motion between the imaging system and the scene are also detected so large GME error or even wrong GME results due to blur images is avoided. This vital function is absent in other GME methods.A hardware architecture implementing this GME method is also developed. High memory bandwidth requirement and irregular memory access are the main challenges for hardware realization of gradient-based GME methods. Block-based data access and processing is proposed to solve these problems. Balanced on-chip memory capacity and off-chip memory bandwidth requirement trade-off is achieved by appropriate memory partition and management strategy. Pipelining, time sharing multiplex access of computation circuit and simplified computation are exploited to increase frame rate, lower memory bandwidth requirement, while reducing area and power consumption at the same time. The memory bandwidth requirement is only 5.9MB/s when performing real-time GME for image sequences with resolution of 352x288 and frequency of 30 Hz, which is much less than similar circuits in the literature.The image pre-processing circuits have finished IP packaging and been integrated into the SoC chip. The chip has finished verification, physical design, tape-out and packaging. Test results show that the IP cores work correctly and fulfill the design goals.