Key-Technologies In Low Power Front-end And Design Of Radio Frequency Transceivers For Bio-medical Applications

Biomedical transceiver is a hot topic in the current wireless communication field.With the continuous development of CMOS technology,the research of low cost and low power monolithic integrated biomedical transceivers has become increasingly important.For the biomedical transceiver,the data transmission is often asymmetric.At the downlink,the transceiver only needs to receive a simple command to control the operation of the external device,and the receiving data rate is low,about hundreds of Kb/s.However,data collected by external devices such as temperature sensors,pressure sensors,or cameras is often very large,which results in a transmitting data rate of several Mb/s.In this paper,a transceiver operating separately in different modes is proposed.The use of low-Q inductance and transformer will bring out the deterioration of the performance of the RF blocks.So how to improve the Q value of the on-chip passive device is a very important topic in the current RF circuit.The non-ideal effect of reducing the Q value is also discussed in details.These technologies to improve the Q include multi-layer metal parallel,PGS technology,the increasing of metal coil width and thickness,the use of low resistivity medium(such as copper)and the increasing of resistance between the metal wire and the substrate.The use of these technologies helps to optimize silicon based passive components.In the circuit design,this paper will focus on the design and implementation of key blocks.As the CMOS process keeps scaling down,the supply voltage is also reduced proportionally,but the threshold voltage is almost unchanged which is the main challenge of the receiver.This paper proposes an energy harvesting circuit with high sensitivity.The circuit is based on the compensation of the gate terminal and improves the input sensitivity of the circuit.The circuit is verified by UMC 0.18 ?.m process,and test results show that the input sensitivity is-10dBm.The output voltage can reach 1.83V when the input voltage is 500mV.The energy harvesting circuit is followed by two LDOs which covers the1.2?12V output range of the energy harvesting circuit.The first LDO combines different temperature coefficient resistors to get zero temperature output voltage,while the PSR enhancement circuit follows the fluctuation of the supply.The LDO is manufactured by HJTC 0.25?m CMOS,and the area of the regulator is only 0.102mm~2 including the bias circuit.The supply voltage is 4?12V while the LDO outputs a voltage of 2.5V.The TRR and VRR are 0.044mV/C and 1.1 mV/V,respectively,with a total quiescent current of 7.5?A.The second LDO utilizes a small resistor of 15 k?,and the voltage reference is based on subthreshold operation to minimize current consumption.The temperature coefficient of voltage reference is also optimized.A zero-pole tracking compensation is used to generate an internal zero that tracks the load current.The design is based on the UMC 0.18 ?m 2P5M process with a core area of 0.0146 mm.The LDO has a maximum load capacitance of 5 mA and a stable output of 1.1 V.The measured undershoot and overshoot are 55 mV and 60 mV,respectively,with a supply voltage of 1.2?4V and a total quiescent current of only 370 nA at 1.2 V supply.The receiver is composed of a low-voltage amplifier,a gain amplifier and a demodulation circuit.The low-voltage amplifier is a low-voltage single transistor LNA,which amplifies the input signal of the ASK signal.The usage of gain amplifier is convenient for demodulation.The ASK demodulation circuit includes envelope detectors,mean value generators and voltage comparator.The receiver front-end design is based on UMC 0.18 ?m 2P5M EEPROM process with a core area of 533 ?mx817 ?m,the supply voltage is 1.1V and it achieves a 55 pJ/bit energy efficiency at 80kbps data rate.The I/Q(inphase and quadraure)generation circuit is an indispensable block for the whole transceiver.In this paper,I/Q signal generation methods are summarized and two kinds of low noise and low power QVCOs are proposed.The first QVCO is based on MOS series coupling(S-QVCO),and the coupling PMOS transistor facilitates the reduction of flicker noise.General use of inductor model in the process library is replaced by a redesigned inductor which adds the N-well isolation to improve the Q,further improving the phase noise performance.The S-QVCO is based on the XMC 55 nm CMOS process and achieves a-118 dBc/Hz phase noise at 1MHz frequency offset,achieving a FoM of-180.88 dB.The second QVCO is based on the transformer feedback current-reuse topology(TC-QVCO),while utilizes the advantages of the low voltage of transformer feedback and low current of current reuse at the same time,thus reducing the power consumption of the circuit.Moreover,the source attenuation resistor decreases the output signal amplitude imbalance.The TC-QVCO circuit is also based on the XMC 55 nm CMOS process,and achieves-112.23 dBc/Hz at 1MHz frequency offset.Consequently the FoM is-178.44 dB and the output voltage amplitude imbalance is 30 mV.In order to meet the strict requirements of low power consumption and high data rate transmission,a phase-selector based FSK modulator is proposed,which is different from the traditional mixer-based transmitter.The modulation rate of mixer-based transmitter is limited by the phase-locked loop(PLL)bandwidth.The modulator operates outside the PLL,eliminating the limitation of the bandwidth and using a phase selector instead of a filter that consumes a large amount of current.The energy efficiency of the transmitter is improved greatly.In order to save the area,the MOS capacitor filter and Ring-VCO are used in the phase-locked loop.According to the principle of phase noise source,the Gaussian white noise and flicker noise of Ring-VCO are deduced,respectively,then the complete phase noise expression of proposed Ring-VCO is obtained.This paper takes advantage of a self-bias circuit to improve the phase noise performance.The self-resonant frequency of the static divider is analyzed,which helps us to know the highest frequency that the divider can operate.The entire chip is based on the UMC 0.18 ?m process,with a core area of only 0.04 mm~2.Measurement result shows that the Ring-VCO achieves-108 dBc/Hz phase noise at the 1MHz frequency offset with a supply voltage of 1.6 V,and the modulator achieves an energy efficiency of 20 pJ/bit at 100 Mbps.