Design Optimization For High-Speed SerDes Physical Layer Based On High-Order Signaling Techniques

With the rapid development of integrated circuit (IC) and constantly improvement on computation capability of multi-processor, chip-to-chip interconnects have become a key point in improving the performance of computer system. Conventional parallel communication method is gradually replaced by high-speed serial communication technique because of the I/O limitation. Nowadays, the physical layer has become a research hotspot of high-speed serial link, which includes equalization technique and signaling method. The variety and complexity of equalizers and constraints in technology make backplane transceiver design challenged by bandwidth, gain, and signal swing, etc. Four-level Pulse Amplitude Modulation (PAM-4) has been applied to the next generation standard for backplane communications due to the bandwidth compression property of PAM-4 symbols. However, there are still several problems for PAM-4, including linearity, pattern-dependent jitter, and the uncertainty of decision thresholds. In this paper, we do the research in equalizer scheme and circuit design, amplitude-modulation technique development, and explorations on phase-modulation technique, all from circuit and system perspectives.Firstly, to cancel the channel-induced inter-symbol interference (ISI), we propose a design method for NRZ-based equalizers. Conventional backplane transceivers exploit the optimization methods on data-rate and power consumption for both transmitter and receiver equalizers. However, we propose a mechanism for allocating performance requirement for each stage of circuits, based on a holistic and systematic perspective. We designed a backplane transceiver circuit targeting 10-16 Gb/s. Multi-corner (including Slow PVT corner, Nominal PVT corner, and Fast PVT corner) simulation results and modeling results reveal that the proposed equalization methods and circuits make about 0.2 UI horizontal eye-opening on three types of channels at BER of 10"12.Secondly, to improve the band-limited serial link, we propose a PAM-4-based transceiver circuit, including linearity-improved symbol generator, transition-aware transmitter equalizer, and digital receiver equalizer. We propose a voltage-mode symbol generator to enhance the output linear range of PAM-4, because the output linearity of the conventional current-mode symbol generator is limited by the input signal. Post-layout simulation on 65 nm CMOS technology shows that the linearity of 10 Gb/s PAM-4 can be improved by 43.1% by using the proposed symbol generator compared with the conventional symbol generator. In addition, a transition-aware feed-forward equalizer (TFFE) for PAM-4 is proposed to reduce the pattern-dependent jitter (PDJ) by changing the transition time of symbols according to the transition type. Post-layout simulation on 65 nm CMOS technology shows that the PDJ of near-end eye diagram can be reduced by half while the far-end eye width can be improved by 0.18 UI at 20 Gb/s with the proposed method. Furthermore, we propose a digital 20 Gb/s PAM-4 4-tap DFE, and the coefficients of DFE can be adapted automatically.Finally, we propose a novel phase-modulation technique, Four-Phase Shifted Sinusoid Symbol (PSS-4), to solve the problem of large SNR penalty in PAM-4. After comparing the SNR and power spectral density of NRZ, PAM-4, and PSS-4, we can conclude that the PSS-4 with pre-emphasis (the duty-cycle of 66%) can get close the PAM-4 on the bandwidth performance, while saving 33% SNR penalty. In addition, we propose a transceiver circuit for PSS-4, including de-cycling, encoder with pre-emphasis, clock recovery, receiver equalizer, and decoder. Transistor-level simulation on 65 nm CMOS technology shows that with the same supply voltage of 1.2 V and transmitter voltage swing of 600 mVp_pd, PSS-4 has twice larger eye height than PAM-4 does in the channels with <20 dB loss at Nyquist frequency. Furthermore, with the supply voltage shrinks from 1.2 V to 0.9 V, the reduction in eye opening of PSS-4 is smaller than that of PAM-4 and NRZ, by 55% and 20%, respectively.This paper explores a design strategy for high-speed serial link in computer systems, from equalizer circuit design and signaling method perspectives. We propose novel circuit design and signaling method for next-generation high-speed inter-chip connection as a reference.