Equalization Techniques For High-speed Serial Link Receiver

With explosive growth of data produced by Big Data,the Internet of Thing(IoT),and Cloud Computing on Internet;and with dramatic demand for high-performance computing system driven by Artificial Intelligence(AI)and self-driving cars,modern computing and storage systems evolute from single-core to multi-core systems.Total input/output(I/O)bandwidths have rapidly scaled to above 10 Gb/s,necessitating a corresponding increase in data transferred between chips or systems.Due to the limited I/O pin count in chip package,high-speed serial link technology becomes one of the most important technologies to improve these parallel computing and storage platforms in both cloud data centers and edge mobile devices.According to Shannon's theorems,the increasing data rate does not come along free.In order to send data faster,bandwidth must be extended.However,in a typical backplane channel,the insertion loss will exceed 30 dB at Nyquist frequency.Because of the limited bandwidth,the transmitted data pulse will not behave as an ideal pulse wave,but with long-tail inter-symbol interference(ISI).To cope with such severe channel impairment,equalization is introduced in SerDes systems,facilitating SerDes systems to operate above 10 Gb/s.In this thesis,the SerDes technology and system architecture are introduced.After that the figure-of-metrics of SerDes system is explained for evaluating the work proposed by this thesis.Secondly,basic equalization theory and equalizer circuit topologies are discussed thoroughly in both frequency domain and time domain.Finally a complete 16Gb/s Receiver with three-stage continuous time linear equalizer(CTLE),7-tap decision feedback equalizer(DFE)is designed and implemented on 22 nm FD-SOI process.And the post-layout simulation shows that the receiver can operate on 16 Gb/s under 0.8V power supply with 18 dB loss channel,achieving an energy efficiency of 2.2mW/Gb/s...