Research On The Stability Of Clock And Data Recovery Circuit Under Radiation Environment

With the applications of audio,video,multi-terminal nodes and other highly integrated services in the field of aerospace,there is a growing demand for wider data bandwidth.It is difficult for traditional data buses,such as RS442 or 1553 B,to meet the requirements of the modern information transmission due to their limited bandwidth.As a result,data buses with higher transmission speed,such as FC-AE,SpaceWire,etc.have come into being.The high-speed buses usually use serial communication technology,and the clock data recovery circuit is one of key modules: firstly,the clock and data recovery(CDR)circuit provides reference clock to the system;secondly,the CDR is used to recover the system clock and retime the data.With the development of the advanced technologies,the space-used CDR circuit faces great challenges:(1)When the data transmission rate is upper than 1Gbps,the data’s width can be compared with the irration pulse.So it’s difficult to distinguish and deal with the transient pulse.SET effect may lead to the recovery clock instability and increase the data error rate;(2)PLL is one of the most basic components in the electronic system and very sensitive to radiation.Affected by SET effect,PLL have the problems of phase shift,clock dithering and even lost lock.To all the block of PLL,the charge pump(CP)and voltage-controlled oscillator(VCO)are the most sensitive circuit to the SET.So we need to pay more attention.This dissertation focuses on the signal stability of CDR circuit in high-speed interface:(1)the selection and stability analysis of CDR circuit under deep sub-micron process;(2)analyze radiation-hardened-by-design(RHBD)under the radiation environment.To solve the first problem,we present a new type of double-loop structure in the CDR and use more digital circuit instead of analog circuit,for the former is easier to harden than the latter.To solve the second problem,we propose a digital control method to filter the SET current pulse,which can cause phase shifting,jitter dithering and other issues.The research work is based on commercial CMOS process,which contributes to localize the aerospace devices and reduce the cost.Furthermore,the third chapter of this paper analyzes the first problem and adopts a phase interpolator structure to propose a dual-loop structure of the clock data recovery circuit.The traditional clock recovery technology is mostly based on the bang-bangstructure digital phase detector.However,for the four quadrature phase clocks participating in the phase discrimination,their rising and falling transition time cannot be completely symmetrical,which could result in different edge time in continuous data sampling or "dead zone" of phase discrimination.Therefore,the recovery clock is ultimately "stable" between a few phases.In other words,the recovery clock may jump among serveral phases.For a digital counter structure,this phenomenon may be stable between the carry and borrow times,which will result in large phase errors.Based on the analysis above,this paper designs the clock control loop and the data delay loop to reduce the dithering of the recovery clock by dynamically stabilizing the final recovery clock between the lower binary phases.For the non-linear phase detector used in clock data recovery,due to the circuit glitch and the too large delay generated by the flip-flop and the XOR gate,and an erroneous pairing indication signal will be generated for a period of time.When the SET occurs,the error may be enlarged.To the problem,a new improved circuit structure is proposed to solve the problem of data phase decision occurring at the same time and the circuit reliability is improved.In addition,Gray code is adopted to reduce the soft errors caused by SET occurring in the clock phase selection control circuit.In terms of decoding,SET pulse filter circuits are designed to improve the overall resistance to soft errors by utilizing the character of data.A variety of meathods are adopted to improve the recovery clock’s stability in the chapter.In the fourth chapter,the second problem is studied.Firstly,the influence of the transient effect of single module in PLL is analyzed.Secondly,a method used to system analysis and simulation is presented.Finally the chapter focuses on the previous research results: charge pump(CP)output stage transistor in PLL circuit is most sensitive to the SET effect,thus,a new circuit structure of Numerical control circuit(NCR)is introduced;the circuit which locates between CP and loop filter(LPF),can completely suppress the current pulse generated by the CP radiation effect during the non-charging or discharging time.Compared with the no-hardened circuits,when the loop is locked,it is found that the 60% current amplitude can be suppressed by using0.75 pC charge injecting the output point of the CP.In the fifth chapter,the verification methods and results are discussed.The conventional no-hardened CDR circuit and the hardened CDR circuit were tested by laser single event radiation in a backside scanning way.The experiment showed that,to the no-hardened cirtuit,when the ion equivalent energy was at 50 MeV.cm222/mg,therecovery clock jittering was intensified at circuit abricated in the 130 nm CMOS process,and when the equivalent energy was at 75 MeV.cm2/mg,latch-up happened.To the hardened CDR circuit,when the ion energy is at 75 MeV.cm22/mg,the clock jittering was exacerbated with SET effect and when the equivalent energy was at 100 MeV.cm222/mg,latch-up happened.Simulation and backside laser test have proven that the SET and SEL(single event latch-up)of hardened CDR circuits are obviously improved.That means hardening of circuits is a very effective approach.