Research On The Key Technologies Of Transceiver Front-end Circuits For UHF RFID Readers

Radio frequency identification（RFID）technology is one of the four basic supporting technologies in the internet of things,which can realize non-contact automatic identification of target objects by wireless communication.With the advantages of long-range,multi-target fast identification,and low cost tags,the passive Ultra-High Frequency（UHF）RFID systems have been widely used in intelligent management information systems such as transportation,warehouse logistics,supply chain,product traceability and so on.In recent years,the continuous expansion of UHF RFID applications has made the need for long-range UHF RFID systems（working distance greater than 10 meters）increasingly urgent,which demands higher sensitivity for UHF RFID readers.On the other hand,in order to promote the large-scale application of UHF RFID system,it is necessary to further reduce the cost,power consumption and size of the reader.The RF transceiver front-end is the core function circuit of the reader,which basically determines the performance of the whole system.The reader based on discrete components can achieve high sensitivity,while it has the disadvantages of high power consumption and large form-factor.At present,the research on reader technologies in academia focuses on the realization methods of low power consumption and fully-integrated reader chip,which are mainly applied to short-range UHF RFID system applications.Therefore,it is of great scientific significance and engineering application value to study the key technologies of miniaturization and high performance transceiver front-end circuits,and to develop low cost,low power and high performance transceiver front-end modules and chips.This dissertation focuses on the key issue that the sensitivity of the UHF RFID reader is limited by the strong RF self-jammer.Based on the systematic analysis of the characteristics and effects of the RF self-jammer,the three aspects of high-performance UHF RFID reader RF front-end circuit,RF transmit-to-receive（TX-to-RX）link isolation structure,and UHF RFID reader RF front-end chip are studied in-depth.The main research works and contributions of the dissertation are as follows:1.To meet the need of miniaturization and high performance applications for RF front-end circuit of the reader,a dual-tuned small-size TX-to-RX isolation structure based on directional coupler is proposed,which improves the rejection of the RF self-jammer significantly.A low-noise receiver front-end architecture is proposed,which can reduce the deterioration of signal to noise ratio（SNR）caused by phase noise of the self-jamming carrier by utilizing range correlation effect.Based on these key techniques,a miniaturized multi-protocol UHF RFID reader module is designed and implemented.The experimental results show that a TX-to-RX isolation of 40⁶5 dB is obtained,and receiver sensitivity of the designed reader module is-86 dBm under an isolation of 50 dB and a bit-rate of 40 kbps,which achieves high performance with a compact size and is suitable for the application of medium-and long-range UHF RFID system.2.Based on the theoretical analysis of the RF self-jammer suppression effect and the impact on the receiver noise figure（NF）of a RF SJC,a RF TX-to-RX isolator based on the cascade of a quadrature-fed circular polarized antenna,a balanced circulator and a passive RF SJC is proposed,which has the advantages of high isolation and low insertion loss.A prototype is designed and the measurement results show that the proposed isolator can suppress the RF self-jammer by 80 dB in the 920-925 MHz frequency band,while the transmission loss of the RX and TX paths is lower than 1.92dB and 1.59 dB,respectively.3.Aiming at the problem of high flicker noise and its effects in RF front-end of UHF RFID reader based on silicon CMOS process,a scheme of RF transceiver front-end with high performance and low noise in silicon-based CMOS process is proposed.Based on TSMC 0.18μm RF CMOS process,a low-noise passive RF SJC based on quadrature digital-to-analog converter is designed,the simulation results show that it achieves more than 40 dB carrier rejection in 900-933 MHz band.A noise and distortion cancelling low-noise transconductance amplifier（LNTA）is proposed,and the linearity of the LNTA is improved by utilizing the complementary second-order nonlinearity coefficients of NMOS and PMOS transistors and the gain expansion of the class-AB amplifier in specific input signal power region,the simulation results show that it achieves an input-referred third-order intercept point（IIP₃）of 18.14 d Bm and an input 1 dB compression point(IP_1dB)of 8.1 dBm.A complementary source follower feedback LNTA is proposed,and the linearity is enhanced by utilizing cancellation effect of the second-order nonlinear distortion in CMOS complementary structure and the derivative superposition linearization technology,the simulation results show that it achieces an IIP₃ and an IP_1dB of 20.8 dBm and 4.14 dBm respectively.A current-mode passive mixer and a trans-impedance amplifier are designed,and a complete inductor-less current-mode receiver RF front-end is realized by combining with the complementary source-follower feedback LNTA.The simulation results show that it achieves a double-sideband noise figure of 16.3 dB and a voltage conversion gain of25.22 dB under the condition of a 0 dBm self-jammer when working with the passive RF SJC,which can improve the reader sensitivity under the condition of a strong self-jammer.4.Aiming at the degradation of reader sensitivity due to the phase noise of the self-jammer,a low phase noise low-voltage g_m-boosted Colpitts voltage-controlled oscillator（VCO）is proposed.A single-ended output swing larger than supply voltage is obtained by removing the tail current source from the traditional Colpitts structure and selecting a small capacitive divider ratio,the phase noise in1 f² region is reduced.Since the proposed VCO has no tail current source and its g_m-boosting transistors operate in switching mode,the up-conversion of the low frequency flicker noise of the transistors is significantly suppressed,the phase noise in1 f³ region is reduced effectively.Designed in TSMC 0.18μm CMOS process,the simulation results show that the proposed VCO can achieve a single-ended peak-to-peak output swing of larger than 1.66 V under a 0.6 V supply voltage,and a frequency tuning range of 3.28³.89GHz.The VCO phase noise at 100 kHz and 1 MHz offset is-104.6 dBc/Hz and-127.6dBc/Hz respectively at 3.76 GHz oscillation frequency,and the1 f³ corner frequency is only 60 kHz.The proposed VCO has the advantage of low phase noise and can be applied to high performance UHF RFID reader chips and other wireless transceiver chips that have stringent requirements for LO phase noise.The research results of this dissertation provide feasible solutions for the realization of high sensitivity UHF RFID reader chips and systems,which can satisfy the extensive application demands of the long-range passive UHF RFID system and help to promote the development of UHF RFID and Internet-of-Things technologies and applications.