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Research And Development Of An Application Specific Integrated Circuit For The Readout Of The Inner Tracker Pixel Detector In ATLAS Phase-? Upgrade

Posted on:2021-01-29Degree:DoctorType:Dissertation
Country:ChinaCandidate:C F ChenFull Text:PDF
GTID:1360330605464290Subject:Radio Physics
Abstract/Summary:PDF Full Text Request
ATLAS,the biggest general-purpose particle detector in the world,is one of the four main detectors on the Large Hadron Collider(LHC)at CERN.It has played a key role in the discovery of the Higgs Boson and made great contribution of the search for theoretical evidence which is beyond the Standard Model in particle physics.Inner Detector is an important part of ATLAS.The high intensity irradiation effect caused by particle collisions will lead to the failure of the electronics system,so the conventional commercial chips cannot meet the requirements of irradiation performance in high energy physics experiments.In addition,present LHC will be upgraded to high luminosity LHC(HL-LHC)in which the luminosity will beincreased to 7*1034cm-2s-1 in the ATLAS Phase-? upgrade project.In this case,the data volumes will become larger and the radiation intensity will be more serious by this higher luminosity.Meanwhile,a new Inner Track Detector(ITk)will replace the existing Inner Detector for it would be not suitable for the upcoming system design plan.Therefore,it is a core target of designing a data transmission link which should have higher irradiation performance,reliability and data rate in the ATLAS Phase-?upgrade project.The main research work of this thesis is to design the data transmission link scheme which is applied to the ITk readout system,and to solve the technical problems during the design.Furthermore,two prototypes of transceiver chips has been designed out for this data link.The fundamental function of this series of chips,which are called GBCR(Gigabit Cable Receiver),is not only to receive and recover the data from the detectors after long distance transmission,but also to send them back to the detectors effectively by using pre-emphasis in advance.So that the data can be transmitted freely through these chips.The details of research work and innovation points in this thesis are as follows.1.A new readout data link scheme has been implemented in the super high radiation environment.The combination of electrical transmission and optical communication is adopted in this new scheme in order to achieve the efficient communication between the front-end module on the detectors and the back-end electronics system through the long distance.Due to the radiation effects,the counting room should keep enough space from the detectors in the data transmission link.In general,the optical communication would be a better option in the large-scale and long-distance data transmission because it has the better bandwidth performance.Since the semiconductor photosensor can not be placed in the super high radiation situation,it is necessary to design an additional electrical link which can connect the detectors and the laser driver.The ASICs in the paper are applied to this electrical link.Although the CMOS device has better irradiation performance than the semiconductor photosensor,but the Single Event Effect(SEE)and the Total Ionizing Dose(TID)still have undesirable effects on them by the hard radiation.So many solutions are adopted to get better irradiation performance in the design,such as using the more advanced commercial 65nm CMOS process,the larger transistor size design and the Enclosed Layout Transistor(ELT).Moreover,the improvements for the SEE robust of all the modules in chips are achieved by using Triple Modular Redundancy(TMR).From the test results,the full data chain can survive under the total ionizing dose of 200 kGy.2.We have solved the key issues of obtaining high peaking strength and wide peaking range in limited area,completed the multi-channel equalizer design with the low mass cable at 5.12 Gbps data rate.At first,the cables have to be low mass to minimize the effects on the calorimeter resolution,but this will lead to the stronger high frequency loss during data transmission.The second,due to the multi-channel requirements,the equalizer should have high peaking strength to compensate the signal loss in limited space.The third,the various of cable types and cable length will cause different high frequency loss.That will request the equalizer should be programmable to adjust the peaking strength to be suitable for all situations.From the test,1 m Flex cable and 6 m Twin-axial AWG34 cable together will make the signals have 24.8 dB loss at 1.28 GHz.The range of equalization is from 8 dB to 30 dB which is tuned by 4 bits.On the other hand,the problem of highly suppressing the DC gain which is caused by the equalizer characteristics itself,can be avoided by using multiple stages of equalizer in series.The minimum value of DC gain is only-5 dB from the AC analysis.At last,a DC offset cancellation circuit in GBCR2,which is low-pass filter structure,can reduce the DC offset significantly.Its low cut-off frequency is far lower than the signal frequency.3.A proposed channel design,which has low power consumption and low jitter,has been made.The scheme makes use of the external clock and high resolution internal phase shifter to implement retiming operation,so that it is not necessary to use Clock Data Recovery(CDR)which has large power consumption.In addition,only one phase shifter can provide 8 different clock signals to each uplink channel in GBCR2,the total power consumption will be significantly reduced in this scheme.The retiming circuit can also effectively suppress the Inter-Symbol Interference(ISI)to meet the requirements of low jitter.Furthermore,the output stage of the uplink channel have programmable tail current.While ensuring the output signal amplitude at the same time,the consumption can be decreased by this structure as well.From the simulation results,GBCR2 just consumes 72 mW,which is 25 percents of GBCR1 and 3.5 percents of commercial equalizer chip LMH0344 in single channel.These two prototypes of GBCR have finished the basic test at present.GBCR1 have passed the irradiation test and the full data chain test especially.The test results are great positive,including highly matching the simulation,having outstanding performance in irradiation,peaking strength and power consumption.The chips almost meet the requirements of specification.
Keywords/Search Tags:High energy physics experiments, High speed data readout link, ASIC, Equalizer
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