| The development of particle detectors has greatly promoted people’s understanding of the microcosmic world.The scalable readout system developed by RD51 can used with different front-end chips for detector readout.The VMM ASIC with high readout rate and good flexibility is a front-end readout chip developed in ATLAS experiment.In order to process more complex and higher energy particle events,RD51 decided to upgrade the front-end electronics of SRS with VMM chip.As the greatly increased data rate of the new readout chip,the SRS FEC firmware cannot handle the so high data rate because of many problems in data processing.Based on this,the high-speed data processing part of SRS FEC firmware has been redesigned to improve the transmission rate and real-time performance of the readout system.Firstly,the VMM chip and other hardware of SRS system are briefly introduced to give the readout hardware transmission link.Then,it analyzes the structure of the FEC firmware,which is the data processing center.And it points out the problem that the original firmware program cannot match the VMM high data readout requirements.Then,the design goals and solutions are put forward and the firmware design of high-speed data readout for the VMM front-end is completed.The main research work is as follows:(1)A new data frame format is designed,which improves the efficiency of data storage and transmission from 59%to 79%.In the original system,the input 38-bit valid hit data formed 64-bit with 26-bit’0’,so the data storage efficiency was only 59%.Adding the loss of each Ethernet frame with additional time and location information,the data transmission efficiency is further reduced.In this thesis,a new 48-bit data format is composed by the original 38-bit hit data with 10-bit used for time and location information,which improves the efficiency of data storage and data transmission.(2)A two-level cache scheme with high-speed FIFO and DDR3 is proposed,which solves the problem of data loss when a large amount of data bursts occur.The buffer used in the original system can only store 512 hits.When the input rate is very high in a short time,the buffer will quickly overflow,resulting in data loss.In this thesis,FIFO and DDR3 are used to form a two-level buffer,which can cache all the high-speed data into the large DDR3 during a time period,avoiding the data loss problem.(3)A solution to improve the real-time performance of data transmission is proposed and implemented.In the original system,every VMM data was cached in a readout cycle,and then all data were loaded into an Ethernet packet to be sent.It has problems in real-time transmission when read out 512 hits at one time per charnnel.In this design,it reads out 1 hit per channel sequentially and sends out Ethernet data package when it is full,which make sure that data caching and readout can work independently and at the same time,and thus effectively improves the real-time data transmission.(4)Triggered readout function is added to improve the utilization of the transmission bandwidth.According to the trigger arrival time and user configurations,the valid event conditions are calculated and analyzed,and according to which the valid event are filtered.There are a lot of invalid events in the physical experiments,so with this function,the transmission efficiency and bandwidth utilization are further improved.In this thesis,the firmware upgrade of the SRS system is implemented,and the logic designed is checked by the Chipscope.After the firmware upgrade,SRS system with new firmware has been tested in laboratory and test beams.The results show that the system works well and stably,and it realizes efficient and real-time transmission.In triggered mode,it filters the valid events effectively. |
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