Circuit-level Compact Models For Single Event Induced Soft Error Evaluation In Nanometer CMOS Integrated Circuits

With the continuous growth of the aerospace industry in our country,radiation hardened integrated circuits(ICs)research develops gradually.The soft error rate(SER)evaluation has become an important way to improve the hardened of ICs in the design stage.With the technology scaling,the conventional SER evaluation approaches are more difficult to obtain an accuracy simulation results due to the complexity of the circuit-level SEE response.Therefore,it is vital to develop new models or approaches to improve the evaluation results.This paper is based on Multi-scaled Monte Carlo simulation approach.We propose some novel circuit-level soft error models to improve the capability of the conventional SER evaluations.This paper presents a physics-based analytical model called PABAM.It is performed to model the bipolar amplification effect in bulk technologies.The proposed PABAM calculate the well potential to determine the triggering of the bipolar amplification effect.Then the charge collection current is calculated to determine the duration of it and the double-exponential current is performed to model the source induced bipolar current.Technologies parameters and layout configurations influence the bipolar amplification effect significantly.The proposed model can take into account these factors.TCAD simulation is performed to confirm the PABAM with different technologies and layout parameters.The simulation results show the same trend with TCAD results.The proposed model is performed to evaluate SEU for twin-and triple-well SRAM.The predicted SEU cross-sections have a good agreement with heavy ion experimental data,especially for MCU prediction.Besides the SRAM circuit,the proposed model will also facilitate the investigation of single event effect in other combinational and sequential circuits.This paper presents a circuit-level process parameter model to evaluate SER variations caused process and operation variations.It is consisted of a series of look-up tables to define the relationship between process or operation variations and the process parameter values.When process or operation conditions change,the process parameter model is used to determine the specific process parameters.Then,the charge collection models could calculate the different transient current with the specific process parameters.The proposed model is validated by TCAD simulation.The calculated collected charge with different process and operation conditions are satisfied with TCAD simulation results.It is also performed to evaluate SEU variations of the sequential circuit cells and SET variations of the combinational circuit cells.The simulated cross sections show good agreement with measurement results,both in magnitude and trend.Simulation results confirm the advantage and the efficiency of the proposed simulation approach.This paper presents a circuit-level model called CLADM.It is performed to evalu-ate TID induced transistor degradations.The proposed model contains two interaction components.The nested sensitive volumes are implemented in the channel/isolation interface regions.It is used to calculate the trapped charge of each sensitive transistor in the first component.TID induced leakage currents are simulated by the additional current source in the second component.The proposed model could improve the capability of the existing circuit-level SER prediction approaches and it can help to evaluate TID induced SER variations in different radiation environments.The proposed model is validated by the TID experiment.The simulated NMOS leakage currents are satisfied with the measurement results.It is also implemented in the existing circuit-level SER simulations to evaluate the SER variations of the commercial SRAM after TID.The simulated SEU cross sections show good agreement with experimental data.Simulation results confirm the advantage of the proposed model.Besides the SRAM circuit,the proposed model will also facilitate the investigation of TID induced degradations in other combinational and sequential circuits.This paper presents a circuit-level charge-pulse model to evaluate SER variations caused by the operation frequency.TCAD tool is performed to determine the relationship between the SET pulse width and the collected charge according to the layout structure.Based on TCAD results,the proposed model is performed to predict SEU caused by the internal SET in the Monte Carlo simulation.Heavy ion experimental results are used to validate the accuracy of the proposed model.Simulation results are consistent with the experimental results.This paper presents a circuit-level simulation approach.It is used to evaluate single-event upset(SEU)of commercial SRAMs and flip-flops.The proposed approach firstly measures the ion-induce sensitive area with different LET values.Then,it calculates the minimum sensitive area which can cause an upset based on the transistor locations in the layout.The proposed approach compares the calculated results with the measured results to determine the SEU characteristics.Heavy ion experiments are used to validate the proposed approach.The simulated SEU cross sections show good agreement with the measured results.