Research On Single Event Effect Hardened Techniques For Standard Cells Of Integrated Circuits Based On 65nm CMOS Process

The aerospace science and technology of our country are developing rapidly,the high performance and anti-radiation integrated circuits(ICs)are very urgent for spacecraft.With the continuous development of semiconductor technology,the size of devices is shrinking,and the node capacitance together with the operating voltage are reducing,the clock frequency is increasing,the Single Event Effect(SEE)is becoming the main reason of soft error of ICs in space.Thus,for nano technology,the research of SEE is very important.Based on 65nm CMOS bulk silicon technology,this paper investigated the influence of process doping on the SEE and the merits and drawbacks of hardened techniques.Then,combined with circuit design and layout design,this paper proposed the radiation-hardened structures of inverter chain,latch and SRAM cell.The main works and contribution of this paper are as follows:(1)This paper studied the influence of N-well doping concentration on single event transient(SET).And we have found that increasing the N-well doping in the appropriate range can reduce the bipolar amplification effect and improve the radiation immunity of PMOS,which will provide guidance for the irradiation ICs design by improving the process.For the isolation technique,the bipolar effect can be mitigated if an ion struck at an OFF-PMOS,and the amplitude of SET pulse that is occurred at the drain of the struck PMOS can be lowered effectively.Nevertheless,if the isolation technique is utilized in circuits,the SET negative pulse may occur when an ON-PMOS is hit by particles.Understanding the isolation technique is meaningful for applying and improving it properly.(2)This paper proposed two inverter chains for the purpose of eliminating the SET pulse.They are dual-output inverter chain and the inverter chain with parallel output nodes.The circuit changing combined with layout optimization design,both the inverter chains can mitigate SET significantly.The simulation results illustrated that the proposed inverter chains manifests an effective improvement of immunity to SET.Besides that,as long as the SET pulse is not generated at the eventual output node,the pulse can be eliminated by the proposed inverter chains.Compared with the conventional inverter chain,the inverter chain with source isolation and the inverter chain with C-element,when the ion strikes with the value of LET is 60MeV·cm2/mg and different directions of angle 60°,the proposed two inverter chains manifest an effective improvement of immunity to SET.(3)This paper put forward a Single Event Upset(SEU)tolerant latch.By means of the parallel nodes structure design together with the layout-level optimization design using the advantages of isolation approach and the charge sharing,the proposed design is capable of substantially improving the immunity to SEU.As compared with the exsiting techniques,when the ion strikes vertically or with different directions of angle 60° with the value of LET is 90MeV cm2/mg,the simulation results demonstrated that the proposed latch has a better performance in SEU mitigation.For P-hit simulation,the proposed latch can hold the storage data and achieve a correct output in the end,no matter the struck PMOS is at OFF state or ON state.For N-hit simulation,the proposed latch is also capable of mitigating the voltage transient and recovering to the original state eventually.(4)This paper proposed a SEU-hardened SRAM cell.We changed the inner topological structure on basis of the Quatro cell and achieved the optimization of layout.Compared with the Quatro cell,the simulation results illustrated that the write speed of our proposed structure has improved 72.7%,and the power consumption has decrese by 70.8%.Morveve,the static noise margins(SNM)are improved significantly.In addition,the SEU threshold of Quatro-10T is just between 1.3MeV·cm2/mg and 1.4MeV cm2/mg,but the proposed latch can still immune SEU and SEMNUs when the value of LET is 60MeV cm2/mg.For the devices and circuits based on CMOS bulk silicon technology,the above research can provide systematic theory and hardened approach of SEE,which is very significant in irradiation ICs designing by process,circuit together with layout improving.