Study And Design On Low Power And Small Area BLE RF Chip

With the massive growth of internet of things（IoT）demand,bluetooth low energy（BLE）technology has become a popular solution for short-distance wireless system.Especially BLE becomes more practical for automation,industrial control,smart family applications when BLE transmission distance is extended.Therefore,BLE technology not only has scientific research significance but also has important application value and broad market prospects.In order to extend the life of the battery,BLE devices usually need to work steadily for a long time.Low energy design is the most important requirement of BLE technology.BLE RF chip is the key chip in BLE system which consumes the largest proportion of power consumption.How to realize low energy and low cost design with the requirements of BLE is one of important topics for researchers.In this thesis,the key techniques of low power and small area of BLE RF chip are studied which focus on the design of the core modules of receiver and transmitter.The designed BLE RF chip was validated by 0.11μm RFCMOS process.The main work and innovation points are as follows:（1）A RF front-end of receiver with shared inductor is proposed.The RF front-end consists of an antenna switch,a matching circuit,an inductor-less low noise amplifier（LNA）,and an active mixer.A two-stage amplification cascade architecture combining current regeneration technique and active inductance technique are adopted in Inductor-less LNA.The first stage of amplification utilizes current regeneration technique for larger transconductance with low power consumption.In the second stage,active inductance is realized by the capacitance C_gs between the gate and source of MOS transistor in the source follower.Simulation results show that in bluetooth working frequency range2.402 GHz².483.5 GHz,the maximum S₁₁ of receiver is-14.5 dB,the maximum S₁₁of transmitter is-17.5 dB,NF is 3.7dB,IIP3 is-15.8dbm,IIP2 is 10 dBm,and the power consumption of receiver’s RF front-end is 1.5 mW.（2）An active RC complex filter circuit with adjustable gain and automatic bandwidth calibration is designed.Gain adjustable range is 0 dB-20 dB.The bandwidth variation due to“corner”problem in CMOS process is reduced by the bandwidth automatic calibration circuit.Calibration range is 30%,and calibration accuracy is 2%.When the chip is powered on,the calibration circuit starts to work.After finishing calibration,the calibration circuit automatically cut off,which will reduce the power consumption of the chip.（3）A scheme for reducing the frequency shift keying error（FSK error）is proposed which automatically reduces the loop gain in the two-point modulation phase-locked loop,resulting in less gain sensitivity of the two loops to the production process,temperature,and environmental factors.The bias current is held constant by a negative feedback network in the voltage-controlled oscillator（VCO）,reducing the VCO low frequency phase noise.The sensitivity of the FSK error to the variation of the variable capacitance process is reduced.The simulation results show that the open-loop phase noise of VCO at 100 KHz,1 MHz and 3 MHz deviating oscillation frequencies are-95.1 dBc/Hz,-115.4 dBc/Hz and-124.9 dBc/Hz respectively,and the power consumption of PLL is2.2mw.（4）A coarse adjustment algorithm is implemented to speed up the locking time of PLL.When the chip is powered on,the capacitor array is coarsely adjusted by the algorithm.After finishing the coarse adjustment,the capacitor array control word and the corresponding BLE frequency are calculated,and the switching channel is automatically changed.The simulation result indicates that the PLL locking time is less than 30μs which speeds up the locking time and reduces the useless power consumption during the locking time of the PLL.The measure results of the proposed design show that in the Bluetooth operating band of2.402 GHz to 2.483.5 GHz,the maximum S₁₁ of transmitter is-10.6 dB,and the maximum S11of receiver is-11.1 dB.The receiver NF is 7 dB,IIP3 is-17.1 dBm,and IIP2 is 9.8 dBm.The PLL locking time is less than 32μs,the VCO can oscillate at 4.8 GHz,and the phase noise measurements at 10 kHz,1 MHz,and 3 MHz from 4.8 GHz are-83 dBc/Hz,-108 dBc/Hz,and-114 dBc/Hz respectively.The sensitivity of receiver is-93 dBm and power consumption is 9.7mW.The transmitter consumes 9.4 mW at 0 dBm output power and the FSK error is 2.97%.The RF front-end area is only 0.24 mm² and the chip area is 3.6 mm².The performance of the RF chip fits well the BLE specification.The results of this thesis can not only be applied in BLE RF circuits,but also be a reference for other RF circuits.