Research On Reliability Evaluation And Design Technology Of Deep Submicron CMOS VLSI

Reliability is an important requirement for almost all integrated circuits(ICs).Especially in the condition of harsh environment,the performance and reliability of ICs are required to have a higher level.Therefore,IC manufacturers have focused on various reliability problems in the process of design and manufacture.With the aggressive scaling of the feature size of CMOS technology,complementary metal oxide semiconductor(CMOS)materials are very close to their intrinsic physical and reliability limits.At deep submicron and nano technology node,reliability challenges have become more and more concerned.Based on the above background,this article researches on the issue that is reliability evaluation and design technology of deep submicron CMOS integrated circuits.Starting from various reliability problems of CMOS ICs,the article focuses on physical model,failure mechanism and test structure of the reliability items including hot carrier effect(HCE),time dependent dielectric breakdown(TDDB),negative bias temperature instability(NBTI),electromigration(EM)and radiation effect.Moreover,an in-depth analysis is conducted on hot carrier effect and TDDB of 65 nm CMOS process,the total ionizing dose(TID)effects of 0.13μm process ferroelectric random access memory(FRAM).The main content in this dissertation include:For the issues of process reliability,the physical models,failure mechanism and test structure of the four failure items which are HCE,TDDB,NBTI and EM are studied in detail.Especially,an in-depth study is conducted on HCE and TDDB.The HCI accelerated life test and HCI life prediction of MOS devices fabricated in a 65 nm CMOS process are carried out.There is a comparative study on the performance degradation of 65 nm NMOSFETs with enclosed gate and two-edged gate layouts under hot carrier injection(HCI).The differences of effects of hot carrier and cold carrier on MOS devices and corresponding physical mechanism are analyzed.Meanwhile,the TDDB accelerated life test and TDDB life prediction of 65 nm MOS devices are finished.An analysis is performed on the characteristics of various factors that affect the TDDB of MOS devices.The effect of substrate hot carrier on TDDB is studied in detail.For the issues of radiation effect of electronic devices,the total ionizing dose(TID)effect of FRAM is investigated.The full chip global irradiation with Co-60 γ ray source is performed.Furthermore,the local irradiation tests with X-ray microbeam from synchrotron and electron accelerator with an aluminum holed-shield are carried out,because Co-60 γ ray source can not perform the local irradiation on FRAM memory cells and peripheral circuits independently.The radiosensitivity and failure mechanism of function blocks in FRAM chip are studied in detail.The differences and application characteristics of different radiation sources are compared and investigated.Based on the detailed study on various reliability issues of deep submicron CMOS integrated circuits,the research on reliability optimal design is performed,including radiation-hardened-by-design(RHBD)technique,HCI hardened by design technique,and methods to improve the reliability of gate dielectric.