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Research On Process Reliability Evaluation Method And Test Application Of Integrated Circuit Gate Dielectric

Posted on:2022-03-21Degree:MasterType:Thesis
Country:ChinaCandidate:T WangFull Text:PDF
GTID:2518306605468224Subject:Microelectronics and Solid State Electronics
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The development of integrated circuits towards high performance and high integration is an inevitable trend,and this goal can be achieved by reducing the feature size of the device.However,the increase in the number of components in the circuit will lead to higher and higher requirements for circuit reliability,especially for circuits that work in harsh environments.Generally speaking,reliability issues are related to circuit design,device structure,and manufacturing process.The most influential one is the manufacturing process level.As the feature size advances to the deep submicron or even nanometer level,some semiconductor materials have approached their physical limits.,The challenge brought to the circuit reliability has also aroused people’s attention.Based on the above background,this article starts with the main failure mechanisms of integrated circuits,and conducts research on the reliability evaluation and test applications of integrated circuits.First,focus on two inherent failure mechanisms related to the gate dielectric of the device:hot carrier injection effect and time-dependent breakdown of the gate dielectric,detailed analysis of their generation mechanism and physical process,and summarized the current reliability evaluation Commonly used device life models provide a model basis for subsequent data analysis.It also introduces the requirements,flow and test methods of process reliability evaluation.Secondly,the process evaluation of the hot carrier injection effect and the breakdown with time is carried out.Generally,people cannot directly obtain the reliability parameters that characterize the process level.Therefore,this paper adopts the evaluation method based on the test structure to evaluate the reliability of the device,Apply the specific test structure designed according to the JEDEC standard,through the wafer-level accelerated stress test,obtain the characteristic parameters of different failure mechanisms,so as to characterize the level of the relevant process line manufacturing level.The hot carrier effect of 0.35μm NMOS devices is studied,the IV test method is used to complete the test,the degradation of leakage current,transconductance,and threshold voltage during the stress duration is analyzed,and the substrate current model is selected to extrapolate the device under normal use conditions The lifetime value is about 0.5 years,which is consistent with the actual measurement results.In addition,it is concluded that the hot carrier degradation is more serious under the high temperature condition of the 0.35μm process node.The time-dependent breakdown effect of 0.13μm CMOS process was studied,combined with the test standards and test objectives of the time-dependent breakdown effect at home and abroad,a test method for evaluating the time-dependent breakdown effect MOS capacitor test structure was developed.Accelerated tests are carried out under voltage stress and temperature,and the life of the device is predicted based on the power exponent model,which proves that the process level meets the requirements for use under normal conditions.At the same time,the time-dependent breakdown characteristics are studied,and the influence of the gate voltage,temperature,and gate oxide area on the time-dependent breakdown effect is analyzed.Finally,considering the flexibility and compatibility of the C# language,visual programming is used to design a data analysis system for automatically processing test results.The "statistical analysis" module is based on the data processing procedures proposed in Chapters 3 and 4,and uses linear regression analysis methods.Substrate current model,drain-source voltage model,substrate/drain current relationship ratio model for hot carrier injection effects,E model,1/E model,gate voltage model,power exponent model,electrical Migrating Black model,negative bias temperature instability α,βmodel,a total of ten models extract model parameters,input the stress under accelerated test and normal working conditions,calculate the acceleration coefficient,and predict the normal working conditions of the device Life.Through the automatic calculation of the test data,the work efficiency is greatly improved,and the purpose of evaluating the manufacturing level of the process line is realized.
Keywords/Search Tags:process reliability evaluation, hot carrier injection, time dependent dielectric breakdown, data analysis system
PDF Full Text Request
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